Taniya Das has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37305 )
Change subject: sc7180: clock: Add support for QUP DFSR configuration ......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37305/1/src/soc/qualcomm/sc7180/clo... File src/soc/qualcomm/sc7180/clock.c:
https://review.coreboot.org/c/coreboot/+/37305/1/src/soc/qualcomm/sc7180/clo... PS1, Line 231: void clock_configure_dfsr(int qup)
This doesn't seem to get called anywhere in this patch train. […]
Hi Julius,
This would be invoked by the QUPv3 firmware driver to enable the QUPv3 SE clocks to dynamic frequency switch mode. The firmware driver is aware of which SEs to be kept in the DFS mode.
The clock driver in kernel would read these registers and re-populate the frequencies supported for the DFS controlled clocks.
Also the GENI driver on the HLOS expects the SEs in DFS mode.
SDM845: I guess there was some portion of the code in the firmware loading code, but it was incomplete.