Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36812 )
Change subject: AGESA,binaryPI: Move SCI enable outside table creation
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Patch Set 1:
Patch Set 1:
If I understand correctly, clearing a SCI is AMD dependent? Intel silicon is free of this flaw?
It's not really a flaw. I am just going through the various places were we have used HAVE_SMI_HANDLER conditional and enforcing some consistency here.
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