[coreboot-gerrit] Change in coreboot[master]: soc/intel/skl: set PEG port state to auto

[Michael Niewöhner (Code Review)]

Hello  Felix Singer, build bot (Jenkins), Nico Huber, Furquan Shaikh, Paul Menzel, Tim Wawrzynczak, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/48304

to look at the new patch set (#5).

Change subject: soc/intel/skl: set PEG port state to auto
......................................................................

soc/intel/skl: set PEG port state to auto

Setting PegXEnable to 1, statically enables the PEG ports, which blocks
the SoC from going to deeper PC states. Instead, set the state to "auto"
(2), so the port gets disabled, when no device was detected.

Note: Currently, this only works with the AST PCI bridge disabled or the
      VGA jumper set to disabled on coreboot, while it works on vendor
      in any case. The reason for this is still unclear.

Test: powertop on X11SSM-F shows SoC in PC8 like on vendor firmware
      instead of just PC3

Signed-off-by: Michael Niewöhner 
Change-Id: I3933a219b77d7234af273217df031cf627b4071f
---
M src/soc/intel/skylake/romstage/romstage.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/48304/5