Michael Niewöhner uploaded patch set #5 to this change.

View Change

soc/intel/skl: set PEG port state to auto

Setting PegXEnable to 1, statically enables the PEG ports, which blocks
the SoC from going to deeper PC states. Instead, set the state to "auto"
(2), so the port gets disabled, when no device was detected.

Note: Currently, this only works with the AST PCI bridge disabled or the
VGA jumper set to disabled on coreboot, while it works on vendor
in any case. The reason for this is still unclear.

Test: powertop on X11SSM-F shows SoC in PC8 like on vendor firmware
instead of just PC3

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I3933a219b77d7234af273217df031cf627b4071f
---
M src/soc/intel/skylake/romstage/romstage.c
1 file changed, 3 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/48304/5

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3933a219b77d7234af273217df031cf627b4071f
Gerrit-Change-Number: 48304
Gerrit-PatchSet: 5
Gerrit-Owner: Michael Niewöhner <foss@mniewoehner.de>
Gerrit-Reviewer: Felix Singer <felixsinger@posteo.net>
Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Furquan Shaikh <furquan@google.com>
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