1 Feb
2020
1 Feb
'20
9:06 p.m.
9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38624 )
Change subject: soc/intel/tigerlake: Configure TCSS xHCI and xDCI ......................................................................
Patch Set 11:
Automatic boot test returned (PASS/FAIL/TOTAL): 3/0/3 Emulation targets: EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/386 EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/385 EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/384
Please note: This test is under development and might not be accurate at all!
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I9c790cce8d6e8dfff84ae5ee4ed6b3379f45cb9b
Gerrit-Change-Number: 38624
Gerrit-PatchSet: 11
Gerrit-Owner: Wonkyu Kim wonkyu.kim@intel.com
Gerrit-Reviewer: Furquan Shaikh furquan@google.com
Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Wonkyu Kim wonkyu.kim@intel.com
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-CC: 9elements QA hardwaretestrobot@gmail.com
Gerrit-CC: Aaron Durbin adurbin@chromium.org
Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net
Gerrit-CC: Pratikkumar V Prajapati pratikkumar.v.prajapati@intel.com
Gerrit-Comment-Date: Sat, 01 Feb 2020 20:06:57 +0000
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