[coreboot-gerrit] Change in ...coreboot[master]: vendorcode/google/chromeos: Add option for using ACPI GPIO pin

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31080

Change subject: vendorcode/google/chromeos: Add option for using ACPI GPIO pin
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vendorcode/google/chromeos: Add option for using ACPI GPIO pin

This new option will have the generated Chrome OS ACPI GPIO table
provide the ACPI GPIO pin number instead of the raw GPIO number.

This is necessary if the OS uses a different numbering for GPIOs
that are reported in ACPI than the actual underlying GPIO number.

For example, if the SOC OS driver declares more pins in an ACPI GPIO
bank than there are actual pins in the hardware it will have gaps in
the number space.

This is a reworked version of 6217e9beff16d805ca833e79a2931bcdb3d02a44
which uses a new option instead of just relying on GENERIC_GPIO_LIB.

BUG=b:120686247
TEST=pass firmware_WriteProtect test on Sarien

Change-Id: I3ad5099b7f2f871c7e516988f60a54eb2a75bef7
Signed-off-by: Duncan Laurie 
---
M src/vendorcode/google/chromeos/Kconfig
M src/vendorcode/google/chromeos/acpi.c
2 files changed, 19 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/31080/1

diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index 26ee31e..2edb46f 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -89,5 +89,17 @@
      on normal boot as well as resume and coreboot is only involved
      in the resume piece w.r.t. the platform hierarchy.

+config CHROMEOS_ACPI_GPIO_GENERATE_PIN
+	bool
+	default n
+	depends on HAVE_ACPI_TABLES && GENERIC_GPIO_LIB
+	help
+	  This option will have the generated Chrome OS ACPI GPIO table
+	  provide the ACPI GPIO pin number instead of the raw GPIO number.
+	  This is necessary if the OS uses a different numbering for GPIOs
+	  that are reported in ACPI.  For example, if the SOC declares more
+	  pins in an ACPI GPIO bank than there are actual pins in the hardware
+	  it will have gaps in the number space.
+
 endif # CHROMEOS
 endmenu
diff --git a/src/vendorcode/google/chromeos/acpi.c b/src/vendorcode/google/chromeos/acpi.c
index 6605809..849f4c3 100644
--- a/src/vendorcode/google/chromeos/acpi.c
+++ b/src/vendorcode/google/chromeos/acpi.c
@@ -15,6 +15,9 @@

#include <arch/acpigen.h>
 #include "chromeos.h"
+#if IS_ENABLED(CONFIG_CHROMEOS_ACPI_GPIO_GENERATE_PIN)
+#include <gpio.h>
+#endif

void chromeos_acpi_gpio_generate(const struct cros_gpio *gpios, size_t num)
 {
@@ -28,7 +31,11 @@
    	acpigen_write_package(4);
    	acpigen_write_integer(gpios[i].type);
    	acpigen_write_integer(gpios[i].polarity);
+#if IS_ENABLED(CONFIG_CHROMEOS_ACPI_GPIO_GENERATE_PIN)
+		acpigen_write_integer(gpio_acpi_pin(gpios[i].gpio_num));
+#else
    	acpigen_write_integer(gpios[i].gpio_num);
+#endif
    	acpigen_write_string(gpios[i].device);
    	acpigen_pop_len();
    }