Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/50138 )
Change subject: soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M ......................................................................
soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M
Added new LPC and IGD device IDs for Alderlake M. Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c
TEST=Check if platform information print is coming properly in coreboot
Change-Id: If33c43da8cbd786261b00742e342f0f01622c607 Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/50138 Reviewed-by: Subrata Banik subrata.banik@intel.com Reviewed-by: Ronak Kanabar ronak.kanabar@intel.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/include/device/pci_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/lpc/lpc.c 4 files changed, 7 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Ronak Kanabar: Looks good to me, approved
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index a3382df..520d403 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3037,6 +3037,7 @@ #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_29 0x549d #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_30 0x549e #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_31 0x549f +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_32 0x5186 #define PCI_DEVICE_ID_INTEL_SPR_ESPI_1 0x1b80
/* Intel PCIE device ids */ @@ -3808,6 +3809,7 @@ #define PCI_DEVICE_ID_INTEL_ADL_GT1_9 0x4619 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2 0x46a0 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 +#define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0
/* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index e3646e0..2666426 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -23,6 +23,7 @@ const char *name; } cpu_table[] = { { CPUID_ALDERLAKE_P_A0, "Alderlake-P A0" }, + { CPUID_ALDERLAKE_M_A0, "Alderlake-M A0" }, };
static struct { @@ -78,6 +79,7 @@ { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_31, "Alderlake-P SKU" }, { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_32, "Alderlake-P SKU" }, { PCI_DEVICE_ID_INTEL_ADP_P_ESPI_33, "Alderlake-P SKU" }, + { PCI_DEVICE_ID_INTEL_ADP_M_ESPI_32, "Alderlake-M SKU" }, };
static struct { @@ -96,6 +98,7 @@ { PCI_DEVICE_ID_INTEL_ADL_GT1_8, "Alderlake GT1" }, { PCI_DEVICE_ID_INTEL_ADL_GT1_9, "Alderlake GT1" }, { PCI_DEVICE_ID_INTEL_ADL_P_GT2, "Alderlake P GT2" }, + { PCI_DEVICE_ID_INTEL_ADL_M_GT1, "Alderlake M GT1" }, };
static inline uint8_t get_dev_revision(pci_devfn_t dev) diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index ca96f35..0920a05 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -296,6 +296,7 @@ PCI_DEVICE_ID_INTEL_ADL_GT1_9, PCI_DEVICE_ID_INTEL_ADL_P_GT2, PCI_DEVICE_ID_INTEL_ADL_S_GT1, + PCI_DEVICE_ID_INTEL_ADL_M_GT1, 0, };
diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index df34f3f..e22518c 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -329,6 +329,7 @@ PCI_DEVICE_ID_INTEL_ADP_M_ESPI_29, PCI_DEVICE_ID_INTEL_ADP_M_ESPI_30, PCI_DEVICE_ID_INTEL_ADP_M_ESPI_31, + PCI_DEVICE_ID_INTEL_ADP_M_ESPI_32, PCI_DEVICE_ID_INTEL_SPR_ESPI_1, 0 };