Jamie Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37189 )
Change subject: soc/intel/cannonlake: Add IccMax limitation for CML U22 ......................................................................
soc/intel/cannonlake: Add IccMax limitation for CML U22
IccMax[IA_CORE] for U22 is 35A. Add a limitation to avoid IccMax setting over 35A in fill_vr_domain_config function.
BUG:b:145094963 BRANCH: None TEST: build coreboot and fsp with enabling fw_debug. Flashed to device and checked the log. IccMax of IA_CORE have been setted correctly.
Change-Id: I2ae8feee3073884109e0d171511c5ac01064ffd7 Signed-off-by: Jamie Chen jamie.chen@intel.com --- M src/soc/intel/cannonlake/vr_config.c 1 file changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/37189/1
diff --git a/src/soc/intel/cannonlake/vr_config.c b/src/soc/intel/cannonlake/vr_config.c index 25270d8..671d93d 100644 --- a/src/soc/intel/cannonlake/vr_config.c +++ b/src/soc/intel/cannonlake/vr_config.c @@ -14,6 +14,9 @@ * */
+#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> #include <fsp/api.h> #include <soc/ramstage.h> #include <soc/vr_config.h> @@ -74,6 +77,8 @@ { FSP_S_CONFIG *vr_params = (FSP_S_CONFIG *)params; const struct vr_config *cfg; + struct device *sa_root; + uint16_t did;
if (domain < 0 || domain >= NUM_VR_DOMAINS) return; @@ -96,4 +101,15 @@ vr_params->VrVoltageLimit[domain] = cfg->voltage_limit; vr_params->AcLoadline[domain] = cfg->ac_loadline; vr_params->DcLoadline[domain] = cfg->dc_loadline; + + /* Limit IA_CORE IccMax if CPU SKU is U22 */ + if (domain == VR_IA_CORE) { + sa_root = pcidev_path_on_root(SA_DEVFN_ROOT); + did = pci_read_config16(sa_root, PCI_DEVICE_ID); + if (did == PCI_DEVICE_ID_INTEL_CML_ULT_2_2 && + cfg->icc_max > VR_CFG_AMP(35)) { + printk(BIOS_DEBUG, "VR_CONFIG: IccMax[IA_CORE] has been limited to 35A\n"); + vr_params->IccMax[domain] = VR_CFG_AMP(35); + } + } }