Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77603?usp=email )
Change subject: mb/siemens/mc_apl2: Set Full Reset Bit into Reset Control Register ......................................................................
mb/siemens/mc_apl2: Set Full Reset Bit into Reset Control Register
With the introduction of a new Linux version a problem has appeared after a software initiated reset via CF9h register. The problem manifests itself in the fact that the Linux kernel does not start after the reboot. The problem is solved by setting bit 3 to 1 in Reset Control Register (I/O port CF9h). This leads to the fact that the PCH will drive SLP_S3 active low in the reset sequence. It leads to the same behavior as in commit 04ea73ee78bc ("siemens/mc_apl3: Set Full Reset Bit into Reset Control Register") explained.
Change-Id: Ibc6d538c939e38732f42995d5ec6c8b61f979a6a Signed-off-by: Mario Scheithauer mario.scheithauer@siemens.com --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c 1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/77603/1
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c index 430e67e..af9e25d 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */
+#include <cf9_reset.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> @@ -17,4 +18,9 @@ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); } } + + /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). When Bit 3 is set to 1 + and then a warm reset is triggered the PCH will drive SLP_S3 active (low). SLP_S3 is + then used on the mainboard to generate the right reset timing. */ + outb(FULL_RST, RST_CNT); }