[coreboot-gerrit] [M] Change in coreboot[master]: drivers/intel/fsp2_0: Update MRC cache in ramstage

[Reka Norman (Code Review)]

Attention is currently required from: Kangheui Won, Tim Wawrzynczak, Paul Menzel, Angel Pons, Sridhar Siricilla, Arthur Heymans, Eric Lai, Ronak Kanabar, Andrey Petrov.

Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67669 )

Change subject: drivers/intel/fsp2_0: Update MRC cache in ramstage
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Patch Set 2:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/67669/comment/f411a8ad_77a230c9 
PS1, Line 18:
> Well, it seems really excessive but I can't come up with a better solution either. […]

The header is defined in src/drivers/intel/fsp2_0/include/fsp/info_header.h. It doesn't have versions of any of the components, only the overall image_revision.