Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32070 )
Change subject: [WIP]mb/*: Migrate sandybridge MRC settings to devicetree.cb ......................................................................
Patch Set 11:
(4 comments)
https://review.coreboot.org/#/c/32070/11/src/mainboard/google/butterfly/devi... File src/mainboard/google/butterfly/devicetree.cb:
https://review.coreboot.org/#/c/32070/11/src/mainboard/google/butterfly/devi... PS11, Line 23: register "spd_addresses" = "{ 0xA0, 0x00,0xA4,0x00 }"
Could this be reused with the native raminit?
Yes
https://review.coreboot.org/#/c/32070/11/src/mainboard/google/butterfly/devi... PS11, Line 27:
Do we need this many tabs?
probably not
https://review.coreboot.org/#/c/32070/11/src/mainboard/google/butterfly/devi... PS11, Line 29: register "usb_port_config" = "{ : /* enabled usb oc pin length */ : { 1, 0, 0x0040 }, /* P0: Right USB 3.0 #1 (no OC) */ : { 1, 0, 0x0040 }, /* P1: Right USB 3.0 #2 (no OC) */ : { 1, 0, 0x0040 }, /* P2: Camera (no OC) */ : { 0, 0, 0x0000 }, /* P3: Empty */ : { 0, 0, 0x0000 }, /* P4: Empty */ : { 0, 0, 0x0000 }, /* P5: Empty */ : { 0, 0, 0x0000 }, /* P6: Empty */ : { 0, 0, 0x0000 }, /* P7: Empty */ : { 0, 4, 0x0000 }, /* P8: Empty */ : { 1, 4, 0x0080 }, /* P9: Left USB 1 (no OC) */ : { 1, 4, 0x0040 }, /* P10: Mini PCIe - WLAN / BT (no OC) */ : { 0, 4, 0x0000 }, /* P11: Empty */ : { 0, 4, 0x0000 }, /* P12: Empty */ : { 0, 4, 0x0000 }, /* P13: Empty */ : }"
Couldn't this be generated from the native USB port settings? Two thirds of these values are exactly […]
no. the future plan is to remove all native USB port settings and only use deviceteee values.
https://review.coreboot.org/#/c/32070/11/src/mainboard/intel/dcp847ske/usb.h File src/mainboard/intel/dcp847ske/usb.h:
PS11:
This file is an attempt to unify USB configs. […]
the idea is to have only devicetree settings