Martin Roth (martinroth@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17330
-gerrit
commit 97678f63eb5e19f6fda88dac0709c045d946dae4 Author: Martin Roth martinroth@google.com Date: Tue Nov 8 16:49:52 2016 -0700
nb/intel/gm45: Use lapic udelay in SMM
This is a follow-on patch to commit 10141c30 - (nb/intel/gm45: Use LAPIC udelay instead of custom version) which removed the custom udelay from everywhere except SMM.
This patch removes it from SMM as well, and gets rid of the gm45/delay.c file.
Needs to be tested: R400, T400, or T500
Change-Id: I7970bb5205f4aa10b38172ab5b9f8bcd6766c4e7 Signed-off-by: Martin Roth martinroth@google.com --- src/northbridge/intel/gm45/Makefile.inc | 2 +- src/northbridge/intel/gm45/delay.c | 86 --------------------------------- 2 files changed, 1 insertion(+), 87 deletions(-)
diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index ac5810b..fdf0012 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -34,6 +34,6 @@ ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c
-smm-$(CONFIG_HAVE_SMI_HANDLER) += delay.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c
endif diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c deleted file mode 100644 index 328c751..0000000 --- a/src/northbridge/intel/gm45/delay.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <cpu/x86/tsc.h> -#include <cpu/x86/msr.h> -#include <cpu/intel/speedstep.h> -#include "delay.h" - -/** - * Intel Core(tm) CPUs always run the TSC at the maximum possible CPU clock - */ -static void _udelay(const u32 us, const u32 numerator, const int total) -{ - u32 dword; - tsc_t tsc, tsc1, tscd; - msr_t msr; - u32 fsb = 0, divisor; - u32 d; /* ticks per us */ - - msr = rdmsr(MSR_FSB_FREQ); - switch (msr.lo & 0x07) { - case 5: - fsb = 400; - break; - case 1: - fsb = 533; - break; - case 3: - fsb = 667; - break; - case 2: - fsb = 800; - break; - case 0: - fsb = 1067; - break; - case 4: - fsb = 1333; - break; - case 6: - fsb = 1600; - break; - } - - msr = rdmsr(0x198); - divisor = (msr.hi >> 8) & 0x1f; - - d = ((fsb * divisor) / numerator) / 4; /* CPU clock is always a quarter. */ - - multiply_to_tsc(&tscd, us, d); - - if (!total) { - tsc1 = rdtsc(); - dword = tsc1.lo + tscd.lo; - if ((dword < tsc1.lo) || (dword < tscd.lo)) { - tsc1.hi++; - } - tsc1.lo = dword; - tsc1.hi += tscd.hi; - } else { - tsc1 = tscd; - } - - do { - tsc = rdtsc(); - } while ((tsc.hi < tsc1.hi) - || ((tsc.hi == tsc1.hi) && (tsc.lo < tsc1.lo))); -} - -void udelay(const u32 us) -{ - _udelay(us, 1, 0); -}