Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/45486 )
Change subject: soc/intel/tigerlake: Set TME upd param based on config ......................................................................
soc/intel/tigerlake: Set TME upd param based on config
Set TmeEnable FSP-M upd based on config.
TEST: TME ENABLE and LOCK bits get set when Tme is enabled.
Signed-off-by: Pratik Prajapati pratikkumar.v.prajapati@intel.com Change-Id: Ia804c88057e17844f055fd852fc0b36cfe316432 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45486 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Georgi pgeorgi@google.com Reviewed-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/tigerlake/romstage/fsp_params.c 1 file changed, 3 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 3957299..dc9caee 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -211,6 +211,9 @@ /* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */ dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE); m_cfg->CpuPcieRpEnableMask = dev && dev->enabled; + + /* Change TmeEnable UPD value according to INTEL_TME Kconfig */ + m_cfg->TmeEnable = CONFIG(INTEL_TME); }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)