[coreboot-gerrit] Change in coreboot[master]: mb/pcengines/apu2/mptable.c: add GNB IOAPIC to MP Table

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39702 )

Change subject: mb/pcengines/apu2/mptable.c: add GNB IOAPIC to MP Table
......................................................................

mb/pcengines/apu2/mptable.c: add GNB IOAPIC to MP Table

Signed-off-by: Michał Żygowski 
Change-Id: I385339761b3e1b5dcadb67b8ca29b1518c2db408
---
M src/mainboard/pcengines/apu2/mptable.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/39702/1

diff --git a/src/mainboard/pcengines/apu2/mptable.c b/src/mainboard/pcengines/apu2/mptable.c
index 36bd340..747e777 100644
--- a/src/mainboard/pcengines/apu2/mptable.c
+++ b/src/mainboard/pcengines/apu2/mptable.c
@@ -15,6 +15,7 @@
 #include <arch/smp/mpspec.h>
 #include <arch/ioapic.h>
 #include <stdint.h>
+#include <northbridge/amd/pi/nb_common.h>
 #include <southbridge/amd/common/amd_pci_util.h>

static void *smp_write_config_table(void *v)
@@ -50,6 +51,11 @@

smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);

+	ioapic_id = (io_apic_read((void *)IO_APIC2_ADDR, 0x00) >> 24);
+	ioapic_ver = (io_apic_read((void *)IO_APIC2_ADDR, 0x01) & 0xFF);
+
+	smp_write_ioapic(mc, ioapic_id, ioapic_ver, (void *)IO_APIC2_ADDR);
+
    /* I/O Ints:    Type    Polarity    Trigger     Bus ID   IRQ    APIC ID PIN# */
 #define IO_LOCAL_INT(type, intr, apicid, pin)				\
    smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));