Vaibhav Shankar (vaibhav.shankar@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16349
-gerrit
commit 5dcc43e37e4d14df55592987e4cbb2c59a62f553 Author: Vaibhav Shankar vaibhav.shankar@intel.com Date: Mon Aug 29 14:03:38 2016 -0700
soc/intel/apollolake: Configure DW0 and DW1 GPIO registers
Implement a macro to calculate DW0 register address for GPIOs. Implement GPIO methods to configure DW0 and DW1 registers.
BUG=chrome-os-partner:55877
Change-Id: I6eaa1fcecf5970b365e3418541c75b9866959f7e Signed-off-by: Vaibhav Shankar vaibhav.shankar@intel.com --- src/soc/intel/apollolake/acpi/gpiolib.asl | 71 ++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/gpio_defs.h | 5 ++ 2 files changed, 76 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi/gpiolib.asl b/src/soc/intel/apollolake/acpi/gpiolib.asl new file mode 100644 index 0000000..a021e1f --- /dev/null +++ b/src/soc/intel/apollolake/acpi/gpiolib.asl @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(_SB) +{ + + /* Get Pad Configuration DW0 register value */ + Method(GPC0, 0x1, Serialized) + { + /* Arg0 - (GpioCommunityAddress + Gpio MMIO_Offset) */ + Store(Arg0, Local0) + OperationRegion(PDW0, SystemMemory, Or (CONFIG_IOSF_BASE_ADDRESS, Local0), 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + TEMP,32 + } + Return(TEMP) + } + + /* Set Pad Configuration DW0 register value */ + Method(SPC0, 0x2, Serialized) + { + /* Arg0 - (GpioCommunityAddress + Gpio MMIO_Offset) */ + /* Arg1 - Value for DW0 register */ + Store(Arg0, Local0) + OperationRegion(PDW0, SystemMemory, Or (CONFIG_IOSF_BASE_ADDRESS, Local0), 4) + Field(PDW0, AnyAcc, NoLock, Preserve) { + TEMP,32 + } + Store(Arg1,TEMP) + } + + /* Get Pad Configuration DW1 register value */ + Method(GPC1, 0x1, Serialized) + { + + /* Arg0 = (GpioCommunityAddress + Gpio MMIO_Offset) + 0x4 */ + Store( Add( Arg0, 0x4), Local0) + OperationRegion(PDW1, SystemMemory, Or (CONFIG_IOSF_BASE_ADDRESS, Local0), 4) + Field(PDW1, AnyAcc, NoLock, Preserve) { + TEMP,32 + } + Return(TEMP) + } + + + /* Set Pad Configuration DW1 register value */ + Method(SPC1, 0x2, Serialized) + { + /* Arg0 - (GpioCommunityAddress + Gpio MMIO_Offset) + 0x4 */ + /* Arg1 - Value for DW1 register */ + + Store( Add( Arg0, 0x4), Local0) + OperationRegion(PDW1, SystemMemory, Or (CONFIG_IOSF_BASE_ADDRESS, Local0), 4) + Field(PDW1, AnyAcc, NoLock, Preserve) { + TEMP,32 + } + Store(Arg1,TEMP) + } +} diff --git a/src/soc/intel/apollolake/include/soc/gpio_defs.h b/src/soc/intel/apollolake/include/soc/gpio_defs.h index 88fa475..c4e6782 100644 --- a/src/soc/intel/apollolake/include/soc/gpio_defs.h +++ b/src/soc/intel/apollolake/include/soc/gpio_defs.h @@ -426,6 +426,11 @@ #define PAD_W(pad) (pad - W_OFFSET) #define PAD_SW(pad) (pad - SW_OFFSET)
+/* calculate GPIO DW0 register address */ +#define PAD_IOSF_MMIO(community, pin) \ + ((GPIO_##community << 16) | \ + (PAD_CFG_BASE | PAD_##community(pin) * 8)) + /* Linux names of the GPIO devices. */ #define GPIO_COMM_N_NAME "INT3452:00" #define GPIO_COMM_NW_NAME "INT3452:01"