[coreboot-gerrit] [M] Change in coreboot[main]: soc/ibm/power9/*: add file structure for SOC

[Sergii Dmytruk (Code Review)]

Attention is currently required from: Felix Held, Felix Singer, Igor Bagnucki, Krystian Hebel, Maciej Pijanowski, Martin L Roth, Michał Kopeć, Michał Żygowski, Paul Menzel.

Sergii Dmytruk has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/67062?usp=email )

Change subject: soc/ibm/power9/*: add file structure for SOC
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Patch Set 34:

(3 comments)

File src/soc/ibm/power9/Kconfig:

https://review.coreboot.org/c/coreboot/+/67062/comment/10c1afec_e81b5c02 :
PS33, Line 5: 	help
            :
> We usually put this after the selects.

Done

File src/soc/ibm/power9/Makefile.mk:

PS33:
> Add a blank line between each of the three stages for better distinction.

Done

File src/soc/ibm/power9/chip.c:

https://review.coreboot.org/c/coreboot/+/67062/comment/9e601fdf_e721a134 :
PS33, Line 8: 	ram_range(dev, /*index=*/0, /*base=*/0, /*size=*/cbmem_top_chipset());
            : 	/* This is for OCC and HOMER images */
            : 	r
> Why document the parameters here? The comments make it less readable and one can look up the functio […]

Well, if you have to look up the declaration to understand what's going on, then version without comments must be less readable.  The problem with `0`s in `ram_range(dev, 0, 0, cbmem_top_chipset());` is that they can mean pretty-much anything, so I tried to make it clearer, but adjusted now for consistency with the rest of the code base.