[coreboot-gerrit] Change in coreboot[master]: arch/x86: Attempt to boot without postcar stage/phase

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34752 )

Change subject: arch/x86: Attempt to boot without postcar stage/phase
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Patch Set 5:
> Patch Set 5:
> > As for this change specifically, I haven't looked into the details just yet. A first glance does indicate it's a little messy and could be cleaned up, but it's very much possible to remove postcar and put the CAR teardown at the first part of ramstage. Now whether that's worth it (commit description is 4ms) in comparison to the support cost is another matter that needs to be weighed.
>
> When postcar support was added, there was a similar question about being able to run ramstage directly from romstage and have ramstage do the tear down which postcar currently does. IIUC, the reason for not doing that was to avoid coherency issues. Is that not a concern anymore? Reference: https://review.coreboot.org/c/coreboot/+/14140/3//COMMIT_MSG#14

is that specific to APL? i don't see any such caching related issue so far even on celeron. Might like to hear from Aaron on this ?