Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42064 )
Change subject: soc/amd/picasso: Split I2c implementation for psp_verstage ......................................................................
soc/amd/picasso: Split I2c implementation for psp_verstage
BUG=b:158124527 TEST=Build & boot psp_verstage on trembyle
Signed-off-by: Martin Roth martin@coreboot.org Change-Id: I45380e0c61e1bb7a94a96630e5867b7ffca0909c --- M src/soc/amd/picasso/Makefile.inc A src/soc/amd/picasso/i2c-psp.c A src/soc/amd/picasso/i2c-x86.c M src/soc/amd/picasso/i2c.c M src/soc/amd/picasso/include/soc/i2c.h 5 files changed, 86 insertions(+), 35 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/42064/1
diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index ce0a7a8..250b9d1 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -13,6 +13,7 @@ bootblock-y += bootblock/pre_c.S bootblock-y += bootblock/bootblock.c bootblock-y += southbridge.c +bootblock-y += i2c-x86.c bootblock-y += i2c.c bootblock-$(CONFIG_PICASSO_UART) += uart.c bootblock-y += tsc_freq.c @@ -21,6 +22,7 @@ bootblock-y += config.c
romstage-y += i2c.c +romstage-y += i2c-x86.c romstage-y += romstage.c romstage-y += gpio.c romstage-y += pmutil.c @@ -37,10 +39,16 @@ verstage-y += i2c.c verstage-y += pmutil.c verstage-y += config.c +ifeq ($(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),y) +verstage-y += i2c-psp.c +else +verstage-y += i2c-x86.c +endif verstage-$(CONFIG_PICASSO_UART) += uart.c verstage-y += tsc_freq.c
ramstage-y += i2c.c +ramstage-y += i2c-x86.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += data_fabric_util.c diff --git a/src/soc/amd/picasso/i2c-psp.c b/src/soc/amd/picasso/i2c-psp.c new file mode 100644 index 0000000..c4840cd --- /dev/null +++ b/src/soc/amd/picasso/i2c-psp.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <commonlib/helpers.h> +#include <console/console.h> +#include <drivers/i2c/designware/dw_i2c.h> +#include <soc/i2c.h> +#include <soc/iomap.h> +#include <stdint.h> + +static uintptr_t i2c_bus_address[I2C_MASTER_DEV_COUNT]; + +uintptr_t dw_i2c_base_address(unsigned int bus) +{ + if (bus >= ARRAY_SIZE(i2c_bus_address)) + return 0; + + return i2c_bus_address[bus]; +} +void i2c_set_bar(unsigned int bus, uintptr_t bar) +{ + if (bus >= ARRAY_SIZE(i2c_bus_address)) { + printk(BIOS_ERR, "Error: i2c index out of bounds: %u.", bus); + return; + } + + i2c_bus_address[bus] = bar; +} diff --git a/src/soc/amd/picasso/i2c-x86.c b/src/soc/amd/picasso/i2c-x86.c new file mode 100644 index 0000000..444a430 --- /dev/null +++ b/src/soc/amd/picasso/i2c-x86.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include <stdint.h> +#include <soc/iomap.h> +#include <commonlib/helpers.h> +#include <drivers/i2c/designware/dw_i2c.h> + +/* + * We don't have addresses for I2C0-1. + */ +static const uintptr_t i2c_bus_address[] = { + 0, + 0, + APU_I2C2_BASE, + APU_I2C3_BASE, + APU_I2C4_BASE, /* Can only be used in slave mode */ +}; + +_Static_assert( + ARRAY_SIZE(i2c_bus_address) == I2C_MASTER_DEV_COUNT + I2C_SLAVE_DEV_COUNT, + "ARRAY_SIZE(i2c_bus_address) must equal I2C_MASTER_DEV_COUNT + I2C_SLAVE_DEV_COUNT"); + +uintptr_t dw_i2c_base_address(unsigned int bus) +{ + if (bus >= ARRAY_SIZE(i2c_bus_address)) + return 0; + + return i2c_bus_address[bus]; +} diff --git a/src/soc/amd/picasso/i2c.c b/src/soc/amd/picasso/i2c.c index 4c8c669..4818455 100644 --- a/src/soc/amd/picasso/i2c.c +++ b/src/soc/amd/picasso/i2c.c @@ -1,40 +1,18 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <device/mmio.h> -#include <acpi/acpi.h> #include <console/console.h> #include <delay.h> -#include <device/device.h> #include <drivers/i2c/designware/dw_i2c.h> #include <amdblocks/acpimmio.h> #include <soc/i2c.h> -#include <soc/iomap.h> -#include <soc/pci_devs.h> +#include <soc/soc_util.h> #include <soc/southbridge.h> #include "chip.h"
/* Global to provide access to chip.c */ const char *i2c_acpi_name(const struct device *dev);
-/* - * We don't have addresses for I2C0-1. - */ -static const uintptr_t i2c_bus_address[I2C_MASTER_DEV_COUNT + I2C_SLAVE_DEV_COUNT] = { - 0, - 0, - APU_I2C2_BASE, - APU_I2C3_BASE, - APU_I2C4_BASE, /* Can only be used in slave mode */ -}; - -uintptr_t dw_i2c_base_address(unsigned int bus) -{ - if (bus >= ARRAY_SIZE(i2c_bus_address)) - return 0; - - return i2c_bus_address[bus]; -} - const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus) { const struct soc_amd_picasso_config *config; @@ -159,7 +137,7 @@ { uint32_t *gpio_ptr;
- gpio_ptr = (uint32_t *)gpio_get_address(gpio); + gpio_ptr = gpio_get_address(gpio); save_table->mux_value = iomux_read8(gpio); save_table->control_value = read32(gpio_ptr); } @@ -169,7 +147,7 @@ { uint32_t *gpio_ptr;
- gpio_ptr = (uint32_t *)gpio_get_address(gpio); + gpio_ptr = gpio_get_address(gpio); iomux_write8(gpio, save_table->mux_value); iomux_read8(gpio); write32(gpio_ptr, save_table->control_value); @@ -180,13 +158,17 @@ void sb_reset_i2c_slaves(void) { const struct soc_amd_picasso_config *cfg; - const struct device *dev = pcidev_path_on_root(GNB_DEVFN); struct soc_amd_i2c_save save_table[saved_pins_count]; uint8_t i, j, control; + /* I2C0-1 is not accessible from the x86. */ + uint32_t *i2c_gpio_ptr[] = { + NULL, + NULL, + gpio_get_address(I2C2_SCL_PIN), + gpio_get_address(I2C3_SCL_PIN), + };
- if (!dev || !dev->chip_info) - return; - cfg = dev->chip_info; + cfg = config_of_soc(); control = cfg->i2c_scl_reset & GPIO_I2C_MASK; if (control == 0) return; @@ -202,19 +184,19 @@ */ for (j = 0; j < 9; j++) { if (control & GPIO_I2C2_SCL) - write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_LOW); + write32(i2c_gpio_ptr[2], GPIO_SCL_LOW); if (control & GPIO_I2C3_SCL) - write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_LOW); + write32(i2c_gpio_ptr[3], GPIO_SCL_LOW);
- read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ + read32(i2c_gpio_ptr[3]); /* Flush posted write */ udelay(4); /* 4usec gets 85KHz for 1 pin, 70KHz for 4 pins */
if (control & GPIO_I2C2_SCL) - write32((uint32_t *)GPIO_I2C2_ADDRESS, GPIO_SCL_HIGH); + write32(i2c_gpio_ptr[2], GPIO_SCL_HIGH); if (control & GPIO_I2C3_SCL) - write32((uint32_t *)GPIO_I2C3_ADDRESS, GPIO_SCL_HIGH); + write32(i2c_gpio_ptr[3], GPIO_SCL_HIGH);
- read32((uint32_t *)GPIO_I2C3_ADDRESS); /* Flush posted write */ + read32(i2c_gpio_ptr[3]); /* Flush posted write */ udelay(4); }
diff --git a/src/soc/amd/picasso/include/soc/i2c.h b/src/soc/amd/picasso/include/soc/i2c.h index 58c27a4..f468d74 100644 --- a/src/soc/amd/picasso/include/soc/i2c.h +++ b/src/soc/amd/picasso/include/soc/i2c.h @@ -27,4 +27,7 @@
void sb_reset_i2c_slaves(void);
+/* Sets the base address for the specific I2C bus. */ +void i2c_set_bar(unsigned int bus, uintptr_t bar); + #endif /* __PICASSO_I2C_H__ */