[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38512 )

Change subject: soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device
......................................................................

soc/intel/skylake: Only reserve TPM area for !CONFIG_TPM_CR50 device

As per PC client TPM specification, the TPM description contains the
base address of the TIS interface 0xfed40000 and the size of
the MMIO area is 20KB (0x5000). Hence ACPI used to reserve those fixed
system memory from getting used by OS.

Platform with TPM_CR50 doesn't require fixed SoC mapped memory hence
additional reservation might not required.

TEST=Build and boot EVE and Soraka to OS.

Change-Id: Id02a2659ce42f705180370000df89d4f6b64afce
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38512
Reviewed-by: Aaron Durbin 
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/skylake/acpi/systemagent.asl
1 file changed, 2 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Aaron Durbin: Looks good to me, approved
  Angel Pons: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl
index 3902b93..c4d8a70 100644
--- a/src/soc/intel/skylake/acpi/systemagent.asl
+++ b/src/soc/intel/skylake/acpi/systemagent.asl
@@ -182,11 +182,13 @@
    			0x00000000, PCH_PRESERVED_BASE_ADDRESS, 0xfe7fffff,
    			0x00000000, PCH_PRESERVED_BASE_SIZE)

+#if !CONFIG(TPM_CR50)
    	/* TPM Area (0xfed40000-0xfed44fff) */
    	DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
    			Cacheable, ReadWrite,
    			0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
    			0x00005000)
+#endif
 })

/* Find PCI resource area in MCRS */