Sindhoor Tilak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43132 )
Change subject: post_code: delete unneeded postcode calls ......................................................................
post_code: delete unneeded postcode calls
This change removes postcode calls that are either duplicated or not needed anymore
Change-Id: I44e94e64585cdaf9f3d6506fc92e1845c39254f1 Signed-off-by: Sindhoor Tilak sindhoor@sin9yt.net --- M src/cpu/intel/car/core2/cache_as_ram.S M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/car/non-evict/exit_car.S M src/cpu/intel/car/p3/cache_as_ram.S M src/cpu/intel/car/p4-netburst/exit_car.S M src/cpu/intel/haswell/romstage.c M src/cpu/qemu-x86/bootblock.c M src/drivers/intel/fsp1_1/romstage.c M src/mainboard/amd/thatcher/bootblock.c M src/northbridge/intel/sandybridge/romstage.c M src/soc/amd/picasso/romstage.c M src/soc/intel/broadwell/romstage/romstage.c 12 files changed, 0 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/43132/1
diff --git a/src/cpu/intel/car/core2/cache_as_ram.S b/src/cpu/intel/car/core2/cache_as_ram.S index c3f81fa..c59cfb4 100644 --- a/src/cpu/intel/car/core2/cache_as_ram.S +++ b/src/cpu/intel/car/core2/cache_as_ram.S @@ -87,7 +87,6 @@ xorl %edx, %edx wrmsr
- post_code(0x24) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr diff --git a/src/cpu/intel/car/non-evict/cache_as_ram.S b/src/cpu/intel/car/non-evict/cache_as_ram.S index 6095126..5f6e9f5 100644 --- a/src/cpu/intel/car/non-evict/cache_as_ram.S +++ b/src/cpu/intel/car/non-evict/cache_as_ram.S @@ -92,7 +92,6 @@ xorl %edx, %edx wrmsr
- post_code(0x24) /* Set Cache-as-RAM mask. */ movl $(MTRR_PHYS_MASK(0)), %ecx rdmsr diff --git a/src/cpu/intel/car/non-evict/exit_car.S b/src/cpu/intel/car/non-evict/exit_car.S index 4cfe75c..b137e77 100644 --- a/src/cpu/intel/car/non-evict/exit_car.S +++ b/src/cpu/intel/car/non-evict/exit_car.S @@ -34,7 +34,6 @@ andl $~1, %eax wrmsr
- post_code(0x32)
/* Return to caller. */ jmp *%esp diff --git a/src/cpu/intel/car/p3/cache_as_ram.S b/src/cpu/intel/car/p3/cache_as_ram.S index 1cb0cc7..56bb5f3 100644 --- a/src/cpu/intel/car/p3/cache_as_ram.S +++ b/src/cpu/intel/car/p3/cache_as_ram.S @@ -49,7 +49,6 @@ andl $(~0x00000cff), %eax wrmsr
- post_code(0x22)
/* Determine CPU_ADDR_BITS and load PHYSMASK high word to %edx. */ movl $1, %eax diff --git a/src/cpu/intel/car/p4-netburst/exit_car.S b/src/cpu/intel/car/p4-netburst/exit_car.S index 5489bb4..d0e3ee0 100644 --- a/src/cpu/intel/car/p4-netburst/exit_car.S +++ b/src/cpu/intel/car/p4-netburst/exit_car.S @@ -25,7 +25,6 @@ andl $(~MTRR_DEF_TYPE_EN), %eax wrmsr
- post_code(0x32)
/* Return to caller. */ jmp *%esp diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index f3090e7..7a666b0 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -46,7 +46,6 @@ if (wake_from_s3) enable_usb_bar();
- post_code(0x3a); params->pei_data->boot_mode = boot_mode;
timestamp_add_now(TS_BEFORE_INITRAM); diff --git a/src/cpu/qemu-x86/bootblock.c b/src/cpu/qemu-x86/bootblock.c index 1b46403e..99b9939 100644 --- a/src/cpu/qemu-x86/bootblock.c +++ b/src/cpu/qemu-x86/bootblock.c @@ -6,7 +6,6 @@
asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist) { - post_code(0x05);
/* Halt if there was a built in self test failure */ if (bist) { diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index cf11179..58206b2 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -100,7 +100,6 @@ .chipset_context = fih, };
- post_code(0x30);
timestamp_add_now(TS_START_ROMSTAGE);
diff --git a/src/mainboard/amd/thatcher/bootblock.c b/src/mainboard/amd/thatcher/bootblock.c index ae76b72..cf23654 100644 --- a/src/mainboard/amd/thatcher/bootblock.c +++ b/src/mainboard/amd/thatcher/bootblock.c @@ -10,7 +10,6 @@
void bootblock_mainboard_early_init(void) { - post_code(0x30); post_code(POST_ROM_SOC_EARLY_INIT);
gpio_100_write8(0x1, 0x98); diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index d2833d7..6278cac 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -78,5 +78,4 @@
northbridge_romstage_finalize(s3resume);
- post_code(0x3f); } diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index f8cff23..ea2c920 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -83,7 +83,6 @@ mainboard_romstage_entry_s3(s3_resume); elog_boot_notify(s3_resume);
- post_code(0x42); u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val);
diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 2493b41..2ab502c 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -34,7 +34,6 @@ { struct romstage_params rp = { 0 };
- post_code(0x30);
/* System Agent Early Initialization */ systemagent_early_init();