[coreboot-gerrit] Change in coreboot[master]: mb/google/volteer/var/voxel: Disable SRCCLKREQ1#

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/46612 )

Change subject: mb/google/volteer/var/voxel: Disable SRCCLKREQ1#
......................................................................

mb/google/volteer/var/voxel: Disable SRCCLKREQ1#

According to the schematic,SRCCLKREQ1# is not connected,so disable it
on voxel.

BUG=b:171279034
BRANCH=volteer
TEST="emerge-volteer coreboot" compiles successfully.

Signed-off-by: Pan Sheng-Liang 
Change-Id: Ibc4f766bd737f30a9ac3c7354d54398e0c36d59d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46612
Reviewed-by: Tim Wawrzynczak 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/volteer/variants/voxel/overridetree.cb
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Sheng-Liang Pan: Looks good to me, but someone else must approve
  Tim Wawrzynczak: Looks good to me, approved

diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
index d7a265b..e8be8e3 100644
--- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb
+++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb
@@ -14,6 +14,9 @@
    	.tdp_pl4 = 105,
    }"

+	# Disable SRCCLKREQ1#
+	register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"
+
    device domain 0 on
    	device ref dptf on
    		chip drivers/intel/dptf