Attention is currently required from: Angel Pons, Martin L Roth, Maximilian Brune, Paul Menzel, Subrata Banik, Tim Wawrzynczak.
Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/66545?usp=email )
Change subject: mb/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC ......................................................................
Patch Set 23:
(6 comments)
File src/mainboard/intel/adlrvp/devicetree_s.cb:
https://review.coreboot.org/c/coreboot/+/66545/comment/9d9c0e47_18ccb7f6 : PS22, Line 2:
I created this tree as base for other Alderlake RVP-S boards because there are a few of them and I w […]
The settings below apply to all ADL-S boards?
File src/mainboard/intel/adlrvp/devicetree_s.cb:
https://review.coreboot.org/c/coreboot/+/66545/comment/0b4f1561_e70ea103 : PS23, Line 4: register "usb2_ports[6]" = "USB2_PORT_MID(OC7)" # USB3/2 Type A port7 : register "usb2_ports[9]" = "USB2_PORT_MID(OC7)" # USB3/2 Type A port10 : register "usb2_ports[10]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port11 : r Add the XHCI device in the devicetree and move them into its scope.
https://review.coreboot.org/c/coreboot/+/66545/comment/fd047a54_f64218ed : PS23, Line 9: # DDI_PORT_A: Combo PHY A # ADL-S RVP UDIMM 1DPC eDP1.4 Connector : # DDI_PORT_1: Combo PHY B # ADL-S RVP UDIMM 1DPC HDMI 1.4b CRLS : # DDI_PORT_2: Combo PHY C # ADL-S RVP UDIMM 1DPC DP1.4a Connector : # DDI_PORT_3: Combo PHY D # ADL-S RVP UDIMM 1DPC HDMI 2.0b ALS : # DDI_PORT_4: Combo PHY E # ADL-S RVP UDIMM 1DPC DP1.4a Connector : # Enable eDP in PortA #TODO test : #register "ddi_portA_config" = "1" : #[DDI_PORT_A] = DDI_ENABLE_HPD : register "ddi_ports_config" = "{ : [DDI_PORT_1] = DDI_ENABLE_HPD, : [DDI_PORT_2] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, : [DDI_PORT_3] = DDI_ENABLE_HPD, : [DDI_PORT_4] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, : }" Add the iGPU device in the devicetree and move them into its scope.
https://review.coreboot.org/c/coreboot/+/66545/comment/3d6c7711_7dd34d1a : PS23, Line 33: [4] = 0, : [5] = 0, Remove, zero by default.
https://review.coreboot.org/c/coreboot/+/66545/comment/344f24f2_98a6f272 : PS23, Line 24: register "sata_salp_support" = "1" : register "sata_ports_enable" = "{ : [4] = 1, : [5] = 1, : [6] = 1, : [7] = 1, : }" : : register "sata_ports_dev_slp" = "{ : [4] = 0, : [5] = 0, : [6] = 1, : [7] = 1, : }" Add the SATA device in the devicetree and move them into its scope.
File src/mainboard/intel/adlrvp/variants/adlrvp_s_ddr5_udimm_1dpc/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/66545/comment/def70c82_87bc5480 : PS23, Line 60: #device ref pcie_rp9 on (doesn't work) : # # PCIE x4 Slot 2 (Document 626352 is wrong here. it states that clk_src should be 16) : # register "pch_pcie_rp[PCH_RP(9)]" = "{ : # .clk_src = 14, : # .clk_req = 14, : # .flags = PCIE_RP_CLK_REQ_DETECT, : # }" : #end Can be removed?