[coreboot-gerrit] Change in coreboot[master]: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design

[Shreesh Chhabbi (Code Review)]

Attention is currently required from: Shreesh Chhabbi, Ravishankar Sarawadi, Duncan Laurie, Alex Levin, Sukumar Ghorai, Raj Astekar, Patrick Rudolph.
Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49766 )

Change subject: soc/intel/tgl: Update S0ix enable mask based on SoC and mainboard design
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Patch Set 39:

(1 comment)

File src/soc/intel/tigerlake/fsp_params.c:

https://review.coreboot.org/c/coreboot/+/49766/comment/64c4821b_ae5dc80f 
PS1, Line 236: 	params->LpmStateEnableMask = (LPM_S0i2_0 | LPM_S0i2_1 | LPM_S0i2_2 | LPM_S0i3_0 | LPM_S0i3_1) & ~config->LpmStateDisableMask;
> line over 96 characters

Corrected.