[coreboot-gerrit] [M] Change in coreboot[master]: mainboard/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC

[Maximilian Brune (Code Review)]

Attention is currently required from: Maximilian Brune.

Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Lean Sheng Tan,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/66545

to look at the new patch set (#11).

Change subject: mainboard/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC
......................................................................

mainboard/intel/adlrvp: Add ADL-S DDR5 UDIMM 1DPC

TEST=Boot ADL-S DDR5 UDIMM 1DPC and check that ramstage is executing

Signed-off-by: Maximilian Brune 
Change-Id: Ic1f62d6dd0b00d26f8c8a71b624ba5fba4c63774
---
M src/mainboard/intel/adlrvp/Kconfig
M src/mainboard/intel/adlrvp/Kconfig.name
M src/mainboard/intel/adlrvp/Makefile.inc
A src/mainboard/intel/adlrvp/devicetree_s.cb
A src/mainboard/intel/adlrvp/early_gpio_s.c
A src/mainboard/intel/adlrvp/gpio_s.c
M src/mainboard/intel/adlrvp/include/baseboard/variants.h
M src/mainboard/intel/adlrvp/memory.c
M src/mainboard/intel/adlrvp/ramstage.c
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
A src/mainboard/intel/adlrvp/variants/adlrvp_s_ddr5_udimm_1dpc/overridetree.cb
11 files changed, 112 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/66545/11