[coreboot-gerrit] Change in coreboot[master]: nb/intel/i440bx: Avoid ROM area

[Keith Hui (Code Review)]

Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41091 )

Change subject: nb/intel/i440bx: Avoid ROM area
......................................................................

nb/intel/i440bx: Avoid ROM area

Declare the ROM area to be read only in ACPI, and excludes it from
ranges available for MMIO.

Change-Id: Iede1452cce8a15f85d70a3c38b4ec9e2d4a54f9e
Signed-off-by: Keith Hui 
---
M src/northbridge/intel/i440bx/acpi/i440bx.asl
M src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
2 files changed, 18 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/41091/1

diff --git a/src/northbridge/intel/i440bx/acpi/i440bx.asl b/src/northbridge/intel/i440bx/acpi/i440bx.asl
index e1e4e61..70c3aaa 100644
--- a/src/northbridge/intel/i440bx/acpi/i440bx.asl
+++ b/src/northbridge/intel/i440bx/acpi/i440bx.asl
@@ -26,10 +26,26 @@
    		0x00100000,         // Address Base
    		0x00000000,         // Address Length
    		_Y00)
+			/* Reserved for firmware flash */
+		    Memory32Fixed (ReadOnly,
+			0x100000000 - CONFIG_ROM_SIZE,	// Address Base
+			CONFIG_ROM_SIZE,		// Address Length
+			_Y01)
    	})
    	CreateDWordField (BUF1, _Y00._LEN, EMLN)  // _LEN: Length
+		CreateDWordField (BUF1, _Y01._BAS, FLSB)  // _BAS: Base

+		/*
+		 * Use ShiftLeft to avoid 64bit constant (for XP).
+		 * This will work even if the OS does 32bit arithmetic, as
+		 * 32bit (0x00000000 - TOM1) will wrap and give the same
+		 * result as 64bit (0x100000000 - TOM1).
+		 */
+
+		/* Top of 4GB */
+		ShiftLeft(0x10000000, 4, Local0)
+		FLSB = Local0 - CONFIG_ROM_SIZE;
    	EMLN = _SB.PCI0.NB.TOM1 - 0x100000;
-		Return (BUF1)
+		Return (BUF1) /* _SB_.MEM1._CRS.BUF1 */
    }
 }
diff --git a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
index e40b1fc..fa5948f 100644
--- a/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
+++ b/src/northbridge/intel/i440bx/acpi/sb_pci0_crs.asl
@@ -61,6 +61,7 @@
     */
    MM1B = _SB.PCI0.NB.TOM1
    ShiftLeft(0x10000000, 4, Local0)
+	Local0 -= CONFIG_ROM_SIZE
    MM1L = Local0 - MM1B

Return(TMP)