Shaunak Saha has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38452 )
Change subject: soc/intel/tigerlake: Add pinmux support ......................................................................
soc/intel/tigerlake: Add pinmux support
TGL UPD value for selecting alternative native function pins. TGL FSP does native pin mux by IP enable UPD and UART0, I2C4, DMIC0, DMIC1, CNVi pins have alternative pin selection for native fucntions. This UPD values are used by FSP for setting alternative pin selecting and mux for these pins.
BUG=b:144680462 BRANCH=none TEST=Build and boot tigerlake rvp board
Change-Id: I51deba87fcd1cde248e0f73757acf97682879090 Signed-off-by: Shaunak Saha shaunak.saha@intel.com --- M src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h 1 file changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/38452/1
diff --git a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h index 62de63f..4fd2169 100644 --- a/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/tigerlake/include/soc/gpio_soc_defs.h @@ -382,4 +382,46 @@ #define TOTAL_GPIO_COMM (COMM_5 + 1) #define TOTAL_PADS 294
+/* + * TGL UPD value for selecting alternative native function pins. + * TGL FSP does native pin mux by IP enable UPD and UART0, I2C4, DMIC0, DMIC1, CNVi pins + * have alternative pin selection for native fucntions. + * This UPD values are used by FSP for setting alternative pin selecting and mux for these pins. + */ + +#define GPIO_VER2_LP_MUXING_SERIALIO_UART0_RXD_GPP_C8 0x190B0208 +#define GPIO_VER2_LP_MUXING_SERIALIO_UART0_RXD_GPP_F1 0x290C0201 +#define GPIO_VER2_LP_MUXING_SERIALIO_UART0_TXD_GPP_C9 0x190B1209 +#define GPIO_VER2_LP_MUXING_SERIALIO_UART0_TXD_GPP_F2 0x290C1202 +#define GPIO_VER2_LP_MUXING_SERIALIO_UART0_RTS_GPP_C10 0x190B220A +#define GPIO_VER2_LP_MUXING_SERIALIO_UART0_RTS_GPP_F0 0x290C2200 +#define GPIO_VER2_LP_MUXING_SERIALIO_UART0_CTS_GPP_C11 0x190B320B +#define GPIO_VER2_LP_MUXING_SERIALIO_UART0_CTS_GPP_F3 0x290C3203 + +#define GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SDA_GPP_H8 0x1947CC08 +#define GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SDA_GPP_D13 0x3948CC0D +#define GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SCL_GPP_H9 0x1947AC09 +#define GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SCL_GPP_D14 0x3948AC0E + +#define GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_S6 0x29460C06 +#define GPIO_VER2_LP_MUXING_DMIC0_CLKA_GPP_A7 0x59420C07 +#define GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_S2 0x29461402 +#define GPIO_VER2_LP_MUXING_DMIC0_CLKB_GPP_A13 0x5942140D +#define GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_S7 0x29460407 +#define GPIO_VER2_LP_MUXING_DMIC0_DATA_GPP_A8 0x59420408 +#define GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_S4 0x29460E04 +#define GPIO_VER2_LP_MUXING_DMIC1_CLKA_GPP_A9 0x59420E09 +#define GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_S3 0x29461603 +#define GPIO_VER2_LP_MUXING_DMIC1_CLKB_GPP_A14 0x5942160E +#define GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_S5 0x29460605 +#define GPIO_VER2_LP_MUXING_DMIC1_DATA_GPP_A10 0x5942060A + +#define GPIO_VER2_LP_MUXING_CNVI_RF_RESET_GPP_A8 0x2942E408 +#define GPIO_VER2_LP_MUXING_CNVI_RF_RESET_GPP_F4 0x194CE404 + +#define GPIO_VER2_LP_MUXING_CNVI_MODEM_CLKREQ_GPP_A9 0x2942E609 +#define GPIO_VER2_LP_MUXING_CNVI_CRF_XTAL_CLKREQ_GPP_A9 0x3942E609 +#define GPIO_VER2_LP_MUXING_CNVI_MODEM_CLKREQ_GPP_F5 0x294CE605 +#define GPIO_VER2_LP_MUXING_CNVI_CRF_XTAL_CLKREQ_GPP_F5 0x394CE605 + #endif