Leroy P Leahy (leroy.p.leahy@intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10653
-gerrit
commit ec43ed773711cf83816770bbc0455b1109d8b56f Author: Lee Leahy leroy.p.leahy@intel.com Date: Wed Jun 24 11:17:54 2015 -0700
soc/intel/common: Restrict common romstage/ramstage code to FSP
Restrict the use of the common romstage/ramstage code to FSP 1.1
BRANCH=none BUG=None TEST=Build and run on cyan/sklrvp
Change-Id: Ifbdb6b4c201560a97617e83d69bf9974f9411994 Signed-off-by: Lee Leahy leroy.p.leahy@intel.com --- src/soc/intel/common/Kconfig | 4 ++++ src/soc/intel/common/romstage.c | 30 ++++++++---------------------- src/soc/intel/common/romstage.h | 6 ------ 3 files changed, 12 insertions(+), 28 deletions(-)
diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 7b88d55..2e930f4 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -73,18 +73,22 @@ config SOC_INTEL_COMMON_FSP_RAM_INIT config SOC_INTEL_COMMON_FSP_ROMSTAGE bool default n + depends on PLATFORM_USES_FSP1_1
config SOC_INTEL_COMMON_RESET bool default n + depends on PLATFORM_USES_FSP1_1
config SOC_INTEL_COMMON_STACK bool default n + depends on PLATFORM_USES_FSP1_1
config SOC_INTEL_COMMON_STAGE_CACHE bool default n + depends on PLATFORM_USES_FSP1_1
config ROMSTAGE_RAM_STACK_SIZE hex "Size of the romstage RAM stack in bytes" diff --git a/src/soc/intel/common/romstage.c b/src/soc/intel/common/romstage.c index 4f449ed..919de83 100644 --- a/src/soc/intel/common/romstage.c +++ b/src/soc/intel/common/romstage.c @@ -85,10 +85,8 @@ asmlinkage void *romstage_main(unsigned int bist, "No Memory Support"));
/* Display FSP banner */ - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) { - printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); - print_fsp_info(params.chipset_context); - } + printk(BIOS_DEBUG, "FSP TempRamInit successful\n"); + print_fsp_info(params.chipset_context);
/* Get power state */ params.power_state = fill_power_state(); @@ -109,10 +107,8 @@ asmlinkage void *romstage_main(unsigned int bist,
top_of_stack = setup_stack_and_mtrrs();
- if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) { - printk(BIOS_DEBUG, "Calling FspTempRamExit API\n"); - timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START); - } + printk(BIOS_DEBUG, "Calling FspTempRamExit API\n"); + timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_START); return top_of_stack; }
@@ -197,12 +193,10 @@ void romstage_common(struct romstage_params *params)
asmlinkage void romstage_after_car(void *chipset_context) { - if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) { - timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END); - printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n"); - soc_after_temp_ram_exit(); - soc_display_mtrrs(); - } + timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END); + printk(BIOS_DEBUG, "FspTempRamExit returned successfully\n"); + soc_after_temp_ram_exit(); + soc_display_mtrrs();
timestamp_add_now(TS_END_ROMSTAGE);
@@ -253,7 +247,6 @@ __attribute__((weak)) void mainboard_romstage_entry( }
/* Save the DIMM information for SMBIOS table 17 */ -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) __attribute__((weak)) void mainboard_save_dimm_info( struct romstage_params *params) { @@ -348,13 +341,6 @@ __attribute__((weak)) void mainboard_save_dimm_info( mem_info->dimm_cnt = index; printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -#else /* CONFIG_PLATFORM_USES_FSP1_1 */ -__attribute__((weak)) void mainboard_save_dimm_info( - struct romstage_params *params) -{ - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); -} -#endif /* CONFIG_PLATFORM_USES_FSP1_1 */
/* Get the memory configuration data */ __attribute__((weak)) int mrc_cache_get_current( diff --git a/src/soc/intel/common/romstage.h b/src/soc/intel/common/romstage.h index 81f32bc..c677095 100644 --- a/src/soc/intel/common/romstage.h +++ b/src/soc/intel/common/romstage.h @@ -23,9 +23,7 @@
#include <stdint.h> #include <arch/cpu.h> -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) #include <fsp_util.h> -#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ #include <soc/intel/common/util.h> #include <soc/pei_data.h> #include <soc/pm.h> /* chip_power_state */ @@ -73,10 +71,8 @@ struct romstage_params { */
void mainboard_check_ec_image(struct romstage_params *params); -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params); -#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ void mainboard_pre_console_init(struct romstage_params *params); void mainboard_romstage_entry(struct romstage_params *params); void mainboard_save_dimm_info(struct romstage_params *params); @@ -91,11 +87,9 @@ void *setup_stack_and_mtrrs(void); void set_max_freq(void); void soc_after_ram_init(struct romstage_params *params); void soc_after_temp_ram_exit(void); -#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new); void soc_memory_init_params(MEMORY_INIT_UPD *params); -#endif /* CONFIG_PLATFORM_USES_FSP1_1 */ void soc_pre_console_init(struct romstage_params *params); void soc_pre_ram_init(struct romstage_params *params); void soc_romstage_init(struct romstage_params *params);