Vladimir Serbinenko (phcoder@gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13660
-gerrit
commit 77487a2076d44ba521df30c637245f6fcde1dd60 Author: Vladimir Serbinenko phcoder@gmail.com Date: Wed Feb 10 02:42:16 2016 +0100
stout: Support native raminit
Change-Id: If64607d40a64ada8cfe4c3ad054be9d6571fc221 Signed-off-by: Vladimir Serbinenko phcoder@gmail.com --- src/mainboard/google/stout/Kconfig | 4 ---- src/mainboard/google/stout/devicetree.cb | 2 ++ src/mainboard/google/stout/romstage.c | 25 +++++++++++++++++++++++++ 3 files changed, 27 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 9dc2649..fdf462b 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -16,10 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_LPC_TPM select INTEL_INT15
-config USE_NATIVE_RAMINIT - bool - default n - config CHROMEOS select CHROMEOS_VBNV_CMOS
diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 1992664..7563bff 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -14,6 +14,8 @@ chip northbridge/intel/sandybridge register "gpu_panel_power_backlight_on_delay" = "2100" # T5: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # TD: 210ms
+ register "max_mem_clock_mhz" = "666" + device cpu_cluster 0 on chip cpu/intel/socket_rPGA989 device lapic 0 on end diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index d7046a3..983988c 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -28,6 +28,7 @@ #include <console/console.h> #include <northbridge/intel/sandybridge/sandybridge.h> #include <northbridge/intel/sandybridge/raminit.h> +#include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> @@ -138,6 +139,12 @@ static void early_ec_init(void) } }
+void mainboard_get_spd(spd_raw_data *spd) +{ + read_spd(&spd[0], 0x50); + read_spd(&spd[2], 0x52); +} + void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { @@ -209,3 +216,21 @@ int mainboard_should_reset_usb(int s3resume) void mainboard_config_superio(void) { } + +const struct southbridge_usb_port mainboard_usb_ports[] = { + /* enabled usb oc pin length */ + {1, 0, 0}, /* P0: USB 3.0 1 (OC0) */ + {1, 0, 0}, /* P1: USB 3.0 2 (OC0) */ + {0, 0, 0}, /* P2: Empty */ + {1, 0, -1}, /* P3: Camera (no OC) */ + {1, 0, -1}, /* P4: WLAN (no OC) */ + {1, 0, -1}, /* P5: WWAN (no OC) */ + {0, 0, 0}, /* P6: Empty */ + {0, 0, 0}, /* P7: Empty */ + {0, 0, 0}, /* P8: Empty */ + {1, 0, 4}, /* P9: USB 2.0 (AUO4) (OC4) */ + {0, 0, 0}, /* P10: Empty */ + {0, 0, 0}, /* P11: Empty */ + {0, 0, 0}, /* P12: Empty */ + {1, 0, -1}, /* P13: Bluetooth (no OC) */ +};