[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: support for PCIe slot & device detect timeout

[Cliff Huang (Code Review)]

Attention is currently required from: Bora Guvendik, Anil Kumar K, Cliff Huang, Subrata Banik, Tim Wawrzynczak.
Hello Bora Guvendik, build bot (Jenkins), Anil Kumar K, Subrata Banik, Tim Wawrzynczak, Eric Lai,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/63942

to look at the new patch set (#7).

Change subject: soc/intel/alderlake: support for PCIe slot & device detect timeout
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soc/intel/alderlake: support for PCIe slot & device detect timeout

add timeout for root port detection and pass to FSP.
add 'slot implemented' flag and pass to FSP.

PcieRpSlotImplemented needs to be set when the root port is set to
hotplug. There is an assertion in FSP checking this.
PcieRpSlotImplemented is updated only when it is built-in as it is
default to slot implemented in FSP.

BRANCH=firmware-brya-14505.B

Signed-off-by: Cliff Huang 
Change-Id: I13feb1d2d67eaba634a3e700685132fba39e1525
---
M src/soc/intel/alderlake/fsp_params.c
M src/soc/intel/common/block/include/intelblocks/pcie_rp.h
2 files changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/63942/7