Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32170 )
Change subject: soc/skl: Update SkipExtGfxScan in UPD from devtree ......................................................................
soc/skl: Update SkipExtGfxScan in UPD from devtree
The SkipExtGfxScan option is defined in the device tree, but doesn`t update the value in the UPD. It uses the default value - 0. This means that the FSP will scan all external graphics devices, in spite of the configuration in devicetree.cb for a specific board.
Patch updates SkipExtGfxScan options in UPD from devicetree.cb. This change affects all boards with skl/kbl processor.
Change-Id: Ie88a41bdf31f7c3e88df6c70c82a1cbf866372c4 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32170 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Nico Huber nico.h@gmx.de --- M src/soc/intel/skylake/romstage/romstage_fsp20.c 1 file changed, 1 insertion(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved
diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index d9b2706..dcfc363 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -354,6 +354,7 @@
/* Set primary graphic device */ soc_primary_gfx_config_params(m_cfg, config); + m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan;
mainboard_memory_init_params(mupd); }