[coreboot-gerrit] Change in ...coreboot[master]: Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/...

[Duncan Laurie (Code Review)]

Duncan Laurie has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32391 )

Change subject: Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML"
......................................................................

Revert "soc/intel/cannonlake: Enable coreboot MP PPI service for WHL/CML"

This reverts commit 41dad286d846819242a84fc65faed2bbb35845ac. The change will make s0ix fail on Sarien/Arcada Platform.

Signed-off-by: Lijian Zhao 
Change-Id: I169bc6f41fba82fcf515267e8e1d08aa5ee2dce4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32391
Reviewed-by: Duncan Laurie 
Reviewed-by: Furquan Shaikh 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/romstage/fsp_params.c
3 files changed, 1 insertion(+), 17 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Duncan Laurie: Looks good to me, approved
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 026aaf2..40b40d6 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -27,8 +27,6 @@
    bool
    default n
    select SOC_INTEL_COMMON_CANNONLAKE_BASE
-	select FSP_PEIM_TO_PEIM_INTERFACE
-	select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
    help
      Intel Whiskeylake support

@@ -36,12 +34,6 @@
    bool
    default n
    select SOC_INTEL_COMMON_CANNONLAKE_BASE
-	# TODO:
-	# Delete FSP_PEIM_TO_PEIM_INTERFACE and
-	# USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI selection
-	# and select PLATFORM_USES_FSP2_1 once FSP support for CML is ready
-	select FSP_PEIM_TO_PEIM_INTERFACE
-	select USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI
    help
      Intel Cometlake support

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 1fd42cd..b8dba18 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -18,9 +18,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <fsp/api.h>
-#include <fsp/ppi/mp_service_ppi.h>
 #include <fsp/util.h>
-#include <intelblocks/mp_init.h>
 #include <intelblocks/xdci.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/pci_devs.h>
@@ -144,9 +142,6 @@
    	params->Usb3OverCurrentPin[i] = 0;
    }

-	if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
-		params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
-
    mainboard_silicon_init_params(params);

/* Set PsysPmax if it is available from DT */
diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c
index 2ad2c93..86160f6 100644
--- a/src/soc/intel/cannonlake/romstage/fsp_params.c
+++ b/src/soc/intel/cannonlake/romstage/fsp_params.c
@@ -65,10 +65,7 @@
    m_cfg->VmxEnable = CONFIG(ENABLE_VMX);

#if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE)
-	if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
-		m_cfg->SkipMpInit = 0;
-	else
-		m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
+	m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
 #endif

/* Set CpuRatio to match existing MSR value */