[coreboot-gerrit] Change in coreboot[master]: soc/intel/baytrail: Add MRC SMBus workaround

[Máté Kukri (Code Review)]

Máté Kukri has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44092 )

Change subject: soc/intel/baytrail: Add MRC SMBus workaround
......................................................................

soc/intel/baytrail: Add MRC SMBus workaround

- The Bay Trail MRC failes to read the SPDs from SMBus.
- Instead the SPDs are read into a buffer and the buffer is passed to
    the MRC.

Change-Id: I7f560d950cb4e4d118f3ee17e6e19e14cd0cc193
Signed-off-by: Mate Kukri 
---
M src/soc/intel/baytrail/romstage/raminit.c
1 file changed, 15 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/44092/1

diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 7e6bcab..836e911 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -115,11 +115,15 @@
    populate_smbios_tables(dram_data, speed, num_channels);
 }

+#define SPD_SIZE 256
+static u8 spd_buf[SPD_SIZE * NUM_CHANNELS];
+
 void raminit(struct mrc_params *mp, int prev_sleep_state)
 {
    int ret;
    mrc_wrapper_entry_t mrc_entry;
    struct region_device rdev;
+	size_t i;

/* Fill in default entries. */
    mp->version = MRC_PARAMS_VER;
@@ -158,8 +162,18 @@
     */
    mrc_entry = (void *)(uintptr_t)CONFIG_MRC_BIN_ADDRESS;

-	if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS)
+	if (mp->mainboard.dram_info_location == DRAM_INFO_SPD_SMBUS) {
+		/* Workaround for broken SMBus support in the MRC */
    	enable_smbus();
+		mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM;
+		for (i = 0; i < NUM_CHANNELS; ++i)
+			if (mp->mainboard.spd_addrs[i]) {
+				i2c_eeprom_read(mp->mainboard.spd_addrs[i],
+					0, SPD_SIZE, &spd_buf[SPD_SIZE * i]);
+				mp->mainboard.dram_data[i] =
+					&spd_buf[SPD_SIZE * i];
+			}
+	}

ret = mrc_entry(mp);