David Guckian (david.guckian@intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12436
-gerrit
commit 3c9aeb2dcaba499988396df4a3b5e269f56c6312 Author: David Guckian david.guckian@intel.com Date: Sat Nov 14 16:01:33 2015 +0000
intel/fsp_model_406dx: Load APs microcode in model_406dx_init
Load microcode to APs when performing model_406dx_init. The updated fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP will not handle the microcode load.
Change-Id: Ib75f860a34c84bf13c0c6c31ebed13e5787f365e Signed-off-by: David Guckian david.guckian@intel.com --- src/cpu/intel/fsp_model_406dx/Kconfig | 2 +- src/cpu/intel/fsp_model_406dx/model_406dx_init.c | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 1c37cc3..30e7e59 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -28,7 +28,7 @@ config CPU_SPECIFIC_OPTIONS select SMP select SSE2 select UDELAY_LAPIC - select SUPPORT_CPU_UCODE_IN_CBFS if HAVE_FSP_BIN + select SUPPORT_CPU_UCODE_IN_CBFS select PARALLEL_CPU_INIT select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c index b25c997..5482e74 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx_init.c +++ b/src/cpu/intel/fsp_model_406dx/model_406dx_init.c @@ -22,6 +22,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> +#include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include "model_406dx.h" @@ -168,6 +169,9 @@ static void model_406dx_init(struct device *cpu) /* Turn on caching if we haven't already */ x86_enable_cache();
+ /* Load microcode */ + intel_update_microcode_from_cbfs(); + /* Clear out pending MCEs */ configure_mca();