Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34928 )
Change subject: intel/fsp_baytrail: Remove uses of #ifndef __PRE_RAM__ ......................................................................
intel/fsp_baytrail: Remove uses of #ifndef __PRE_RAM__
Either the files are only built for ramstage, or garbage collection takes care of it otherwise.
Change-Id: Id295227df344fb209d7d5fd12e82aa450198bbb8 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/drivers/intel/fsp1_0/fsp_util.c M src/drivers/intel/fsp1_0/fsp_util.h M src/soc/intel/fsp_baytrail/gpio.c M src/soc/intel/fsp_baytrail/include/soc/baytrail.h M src/soc/intel/fsp_baytrail/include/soc/romstage.h M src/soc/intel/fsp_baytrail/romstage/report_platform.c M src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c 7 files changed, 1 insertion(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/34928/1
diff --git a/src/drivers/intel/fsp1_0/fsp_util.c b/src/drivers/intel/fsp1_0/fsp_util.c index d787c7b..c6c88cf 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.c +++ b/src/drivers/intel/fsp1_0/fsp_util.c @@ -25,7 +25,6 @@ #include <cpu/intel/microcode.h> #include <cf9_reset.h>
-#ifndef __PRE_RAM__ /* Globals pointers for FSP structures */ void *FspHobListPtr = NULL; FSP_INFO_HEADER *fsp_header_ptr = NULL; @@ -60,9 +59,6 @@ if (Status != 0) printk(BIOS_ERR,"FSP API NotifyPhase failed for phase 0x%x with status: 0x%x\n", Phase, Status); } -#endif /* #ifndef __PRE_RAM__ */ - -#ifdef __PRE_RAM__
/* The FSP returns here after the fsp_early_init call */ static void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) @@ -115,7 +111,6 @@ /* Should never return. Control will continue from ContinuationFunc */ die("Uh Oh! FspInitApi returned"); } -#endif /* __PRE_RAM__ */
volatile u8 *find_fsp() { @@ -225,8 +220,6 @@ } #endif /* FSP_RESERVE_MEMORY_SIZE */
-#ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ - void print_fsp_info(void) {
if (fsp_header_ptr == NULL) @@ -249,7 +242,6 @@ (u8)(fsp_header_ptr->ImageRevision & 0xff)); }
- #if CONFIG(ENABLE_MRC_CACHE) /** * Save the FSP memory HOB (mrc data) to the MRC area in CBMEM @@ -363,4 +355,3 @@ /* Update the MRC/fast boot cache as part of the late table writing stage */ BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, find_fsp_hob_update_mrc, NULL); -#endif /* #ifndef __PRE_RAM__ */ diff --git a/src/drivers/intel/fsp1_0/fsp_util.h b/src/drivers/intel/fsp1_0/fsp_util.h index e09bbd9..a02e34d 100644 --- a/src/drivers/intel/fsp1_0/fsp_util.h +++ b/src/drivers/intel/fsp1_0/fsp_util.h @@ -79,9 +79,7 @@
struct mrc_data_container *find_current_mrc_cache(void);
-#if !defined(__PRE_RAM__) void update_mrc_cache(void *unused); -#endif
#endif
@@ -99,9 +97,7 @@ #define ERROR_INFO_HEAD_SIG_MISMATCH 5 #define ERROR_FSP_SIG_MISMATCH 6
-#ifndef __PRE_RAM__ extern void *FspHobListPtr; -#endif
#define UPD_DEFAULT_CHECK(member) \ if (config->member != UPD_DEFAULT) { \ diff --git a/src/soc/intel/fsp_baytrail/gpio.c b/src/soc/intel/fsp_baytrail/gpio.c index 6da1258..3e2499a 100644 --- a/src/soc/intel/fsp_baytrail/gpio.c +++ b/src/soc/intel/fsp_baytrail/gpio.c @@ -29,13 +29,11 @@ * PCU iLB GPIO CFIO_SCORE Address Map * PCU iLB GPIO CFIO_SSUS Address Map */ -#ifndef __PRE_RAM__ static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = { 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */ 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */ 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */ 2, 5, 9 }; /* [24:26] */ -#endif
static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] = { 85, 89, 93, 96, 99, 102, 98, 101, /* [ 0: 7] */ @@ -61,8 +59,6 @@ 52, 53, 59, 40 }; /* [40:43] */
-#ifndef __PRE_RAM__ - /* GPIO bank descriptions */ static const struct gpio_bank gpncore_bank = { .gpio_count = GPNCORE_COUNT, @@ -253,7 +249,6 @@ printk(BIOS_DEBUG, "Default/empty GPIO config\n"); return NULL; } -#endif /* #ifndef __PRE_RAM__ */
/** \brief returns the input / output value from an SCORE GPIO * diff --git a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h index 34831b1..fa2f508 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/baytrail.h +++ b/src/soc/intel/fsp_baytrail/include/soc/baytrail.h @@ -51,7 +51,6 @@ int bridge_silicon_revision(void); void rangeley_early_initialization(void);
-#ifndef __PRE_RAM__ /* soc.c */ int soc_silicon_revision(void); int soc_silicon_type(void); @@ -60,7 +59,6 @@
void report_platform_info(void);
-#endif /* __PRE_RAM__ */ #endif /* __ASSEMBLER__ */
#endif /* __ACPI__ */ diff --git a/src/soc/intel/fsp_baytrail/include/soc/romstage.h b/src/soc/intel/fsp_baytrail/include/soc/romstage.h index 5f0bd8d..1f318b3 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/romstage.h +++ b/src/soc/intel/fsp_baytrail/include/soc/romstage.h @@ -21,8 +21,6 @@ #error "Don't include romstage.h from a ramstage compilation unit!" #endif
-void report_platform_info(void); - #include <stdint.h> #include <drivers/intel/fsp1_0/fsp_util.h>
diff --git a/src/soc/intel/fsp_baytrail/romstage/report_platform.c b/src/soc/intel/fsp_baytrail/romstage/report_platform.c index 98f35f0..2b5dad7 100644 --- a/src/soc/intel/fsp_baytrail/romstage/report_platform.c +++ b/src/soc/intel/fsp_baytrail/romstage/report_platform.c @@ -17,7 +17,7 @@ #include <console/console.h> #include <device/pci_ops.h> #include <soc/iosf.h> -#include <soc/romstage.h> +#include <soc/baytrail.h> #include <cpu/x86/msr.h> #include <soc/msr.h> #include <cpu/x86/name.h> diff --git a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c index ba56543..bbcf753 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c +++ b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsphob.c @@ -43,9 +43,7 @@ // // Pointer to the HOB should be initialized with the output of FSP INIT PARAMS // -#ifndef __PRE_RAM__ extern volatile void *FspHobListPtr; -#endif
/** Reads a 64-bit value from memory that may be unaligned. @@ -116,12 +114,8 @@ VOID ) { -#ifndef __PRE_RAM__ ASSERT (FspHobListPtr != NULL); return ((VOID *)FspHobListPtr); -#else - return ((VOID *)NULL); -#endif }
/**