[coreboot-gerrit] Change in coreboot[master]: soc/baytrail: hook up smmstore

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/39190 )

Change subject: soc/baytrail: hook up smmstore
......................................................................

soc/baytrail: hook up smmstore

Adapted from implementation in sb/intel/common.

Test: build/boot variants of google/rambi with Tianocore
and SMMSTORE enabled

Change-Id: Id8adeda982feba1cbcf5e04cf0bef0a6710ad4f0
Signed-off-by: Matt DeVillier 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39190
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/soc/intel/baytrail/smihandler.c
1 file changed, 25 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/baytrail/smihandler.c b/src/soc/intel/baytrail/smihandler.c
index 3a096e3..b8226c2 100644
--- a/src/soc/intel/baytrail/smihandler.c
+++ b/src/soc/intel/baytrail/smihandler.c
@@ -24,6 +24,7 @@
 #include <elog.h>
 #include <halt.h>
 #include <spi-generic.h>
+#include <smmstore.h>

#include <soc/iosf.h>
 #include <soc/pci_devs.h>
@@ -282,6 +283,26 @@
    LPSS_ACPI_MODE_DISABLE(SPI);
 }

+static void southbridge_smi_store(void)
+{
+	u8 sub_command, ret;
+	em64t100_smm_state_save_area_t *io_smi =
+		smi_apmc_find_state_save(APM_CNT_SMMSTORE);
+	uint32_t reg_ebx;
+
+	if (!io_smi)
+		return;
+	/* Command and return value in EAX */
+	sub_command = (io_smi->rax >> 8) & 0xff;
+
+	/* Parameter buffer in EBX */
+	reg_ebx = io_smi->rbx;
+
+	/* drivers/smmstore/smi.c */
+	ret = smmstore_exec(sub_command, (void *)reg_ebx);
+	io_smi->rax = ret;
+}
+
 static void southbridge_smi_apmc(void)
 {
    uint8_t reg8;
@@ -334,6 +355,10 @@
    case APM_CNT_LEGACY:
    	soc_legacy();
    	break;
+	case APM_CNT_SMMSTORE:
+		if (CONFIG(SMMSTORE))
+			southbridge_smi_store();
+		break;
    }

mainboard_smi_apmc(reg8);