Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )
Change subject: Add Intel SkyLake Scalable Processor support ......................................................................
Patch Set 6:
(4 comments)
The alignments in the ASL files need to be fixed and be consistent (tabs for indentation?).
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi.c:
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... PS6, Line 159: int gsi_bases[] = {0, 0x18, 0x20, 0x28, 0x30, 0x48, 0x50, 0x58, 0x60}; Space after {?
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi/globalnvs.asl:
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... PS6, Line 52: PM1I, 64, // 0x15 - PM1 wake status bit Align?
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... File src/soc/intel/skylake_sp/acpi/pci_irq.asl:
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... PS6, Line 25: * https://bugs.acpica.org/show_bug.cgi?id=1201 From the report:
Fixed in ACPICA version 20151124
Please update and remove the comment.
https://review.coreboot.org/c/coreboot/+/38548/6/src/soc/intel/skylake_sp/ac... PS6, Line 83: IRQ (Level, ActiveLow, Shared) {} \ Align.