[coreboot-gerrit] Change in coreboot[master]: soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSP

[Nico Huber (Code Review)]

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34167 )

Change subject: soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSP
......................................................................

soc/intel/cnl: Sync CONFIG_LPSS_UART_FOR_CONSOLE with FSP

We got rid of the dangerous reconfiguration of arbitrary pads in
coreboot, but FSP still overrode that. Make sure that it doesn't
enable a UART for debug output when it isn't configured in core-
boot.

This, again, shows how dangerous it is to leave any FSP UPD at
its binary default.

Change-Id: I7280a80f71ddddbe78352eb696e6f5844d2df0b2
Signed-off-by: Nico Huber 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34167
Tested-by: build bot (Jenkins) 
Reviewed-by: Paul Menzel 
Reviewed-by: Angel Pons 
---
M src/soc/intel/cannonlake/fsp_params.c
1 file changed, 3 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Paul Menzel: Looks good to me, but someone else must approve
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index a58a97c..2367045 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -285,6 +285,9 @@

/* Set Debug serial port */
    params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
+#if !CONFIG(SOC_INTEL_COMETLAKE)
+	params->SerialIoEnableDebugUartAfterPost = CONFIG_INTEL_LPSS_UART_FOR_CONSOLE;
+#endif

/* Enable CNVi Wifi if enabled in device tree */
    dev = pcidev_path_on_root(PCH_DEVFN_CNViWIFI);