[coreboot-gerrit] Change in coreboot[master]: sb/intel/i82801gx/early_init: Use pci_update_config

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41632 )

Change subject: sb/intel/i82801gx/early_init: Use pci_update_config
......................................................................

sb/intel/i82801gx/early_init: Use pci_update_config

Change-Id: Ibe5a6cab384594ef023abd7dc9246c0d7bd7c8c4
Signed-off-by: Elyes HAOUAS 
---
M src/southbridge/intel/i82801gx/early_init.c
1 file changed, 4 insertions(+), 15 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/41632/1

diff --git a/src/southbridge/intel/i82801gx/early_init.c b/src/southbridge/intel/i82801gx/early_init.c
index a913873..b2963b5 100644
--- a/src/southbridge/intel/i82801gx/early_init.c
+++ b/src/southbridge/intel/i82801gx/early_init.c
@@ -61,9 +61,6 @@
 #if ENV_ROMSTAGE
 void i82801gx_early_init(void)
 {
-	uint8_t reg8;
-	uint32_t reg32;
-
    enable_smbus();

/* Setting up Southbridge. In the northbridge code. */
@@ -84,22 +81,14 @@
    pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20);

/* reset rtc power status */
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
-	reg8 &= ~RTC_BATTERY_DEAD;
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
+	pci_update_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, ~RTC_BATTERY_DEAD, 0);

/* USB transient disconnect */
-	reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
-	reg8 |= (3 << 0);
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+	pci_update_config8(PCI_DEV(0, 0x1f, 0), 0xad, ~0, (3 << 0));

-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
-	reg32 |= (1 << 29) | (1 << 17);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+	pci_update_config32(PCI_DEV(0, 0x1d, 7), 0xfc, ~0, (1 << 29) | (1 << 17));

-	reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
-	reg32 |= (1 << 31) | (1 << 27);
-	pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+	pci_update_config32(PCI_DEV(0, 0x1d, 7), 0xdc, ~0, (1 << 31) | (1 << 27));

/* Enable IOAPIC */
    RCBA8(OIC) = 0x03;