Saurabh Satija (saurabh.satija@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15025
-gerrit
commit 972d1d61812ae1b242d7605e37f44f205b9755ba Author: Saurabh Satija saurabh.satija@intel.com Date: Thu Mar 31 15:41:30 2016 -0700
apollolake/amenia: Add NHLT table region to ACPI global nvs
Adding address and length of NHLT table in ACPI.
Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a Signed-off-by: Saurabh Satija saurabh.satija@intel.com --- src/soc/intel/apollolake/acpi/globalnvs.asl | 4 +++- src/soc/intel/apollolake/include/soc/nvs.h | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 2ef5031..3efca51 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -26,8 +26,10 @@ External (NVSA) OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { - /* Nothing here yet, folks */ + /* Miscellaneous */ Offset (0x00), + NHLA, 64, // 0x00 - NHLT Address + NHLL, 32, // 0x08 - NHLT Length
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 8b3a3af..23e40e8 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -28,7 +28,9 @@
struct global_nvs_t { /* Miscellaneous */ - uint8_t unused[256]; + u64 nhla; /* 0x00 - NHLT Address */ + u32 nhll; /* 0x08 - NHLT Length */ + uint8_t unused[244];
/* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;