Attention is currently required from: Arthur Heymans, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel.
Hello Arthur Heymans, Fred Reitberger, Jason Glenesk, Matt DeVillier, Raul Rangel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/75933?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed: Code-Review+1 by Arthur Heymans, Code-Review+1 by Fred Reitberger, Verified+1 by build bot (Jenkins)
Change subject: soc/amd/common/block/acpi/ivrs: conditionally generate eMMC entry ......................................................................
soc/amd/common/block/acpi/ivrs: conditionally generate eMMC entry
The eMMC entry in the IVRS table should only be generated if an eMMC controller is present in the SoC.
Where the PCI_DEVFN(0x13, 1) is from is currently unclear to me. There is no PCI device 0x13 on bus 0 and the eMMC controller is also an MMIO device and not a PCI device, but this is what the reference code does. My guess would be that it mainly needs to be a unique PCI device that won't collide with any existing PCI device in the SoC. Add a comment about this too.
TEST=None
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I00865cb7caf82547e89eb5e77817e3d8ca5d35dd --- M src/soc/amd/common/block/acpi/ivrs.c 1 file changed, 9 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/75933/2