Hello Kyösti Mälkki, build bot (Jenkins), Nico Huber,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/33174
to look at the new patch set (#7).
Change subject: nb/intel/sandybridge/mrc.bin: Increase the CAR size ......................................................................
nb/intel/sandybridge/mrc.bin: Increase the CAR size
The heap/pool of the mrc.bin falls in an awkward location, close to the bottom of the CAR location, which easily conflicts with other CAR linker symbols. To work around this issue, increase the CAR with 128k to a total of 256k, align the base and make sure the heap/pool of the mrc.bin falls in the DCACHE_RAM_MRC_VAR_SIZE.
TESTED on Thinkpad X220. All sandy-/ivy-bridge CPUs ought to have enough cache for this change.
Change-Id: Ida8ad9a54d29a9ee1301bdcff00d81f548d2b81e Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/arch/x86/car.ld M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit_mrc.c 3 files changed, 10 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/33174/7