[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge: Store CPUID in ctrl struct

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39720 )

Change subject: nb/intel/sandybridge: Store CPUID in ctrl struct
......................................................................

nb/intel/sandybridge: Store CPUID in ctrl struct

Instead of storing an int with a single bit of information taken from
the CPUID, we might as well store the actual CPUID.

Tested on Asus P8Z77-V LX2, still boots fine.

Change-Id: I6ac435fb83900a52890f823e7614055061299e23
Signed-off-by: Angel Pons 
---
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_common.h
2 files changed, 6 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/39720/1

diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c
index 34fb499..d332a47 100644
--- a/src/northbridge/intel/sandybridge/raminit.c
+++ b/src/northbridge/intel/sandybridge/raminit.c
@@ -229,7 +229,7 @@

static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size)
 {
-	if (ctrl->sandybridge)
+	if (IS_SANDY_CPU(ctrl->cpu))
    	return try_init_dram_ddr3_snb(ctrl, fast_boot, s3resume, me_uma_size);
    else
    	return try_init_dram_ddr3_ivb(ctrl, fast_boot, s3resume, me_uma_size);
@@ -242,7 +242,6 @@
    spd_raw_data spds[4];
    struct region_device rdev;
    ramctr_timing *ctrl_cached;
-	u32 cpu;

MCHBAR32(SAPMCTL) |= 1;

@@ -315,8 +314,7 @@
    	ctrl.tCK = min_tck;

/* Get architecture */
-		cpu = cpu_get_cpuid();
-		ctrl.sandybridge = IS_SANDY_CPU(cpu);
+		ctrl.cpu = cpu_get_cpuid();

/* Get DDR3 SPD data */
    	memset(spds, 0, sizeof(spds));
@@ -336,8 +334,7 @@
    	ctrl.tCK = min_tck;

/* Get architecture */
-		cpu = cpu_get_cpuid();
-		ctrl.sandybridge = IS_SANDY_CPU(cpu);
+		ctrl.cpu = cpu_get_cpuid();

/* Reset DDR3 frequency */
    	dram_find_spds_ddr3(spds, &ctrl);
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index 0735cea..0047158 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -76,7 +76,9 @@

typedef struct ramctr_timing_st {
    u16 spd_crc[NUM_CHANNELS][NUM_SLOTS];
-	int sandybridge;
+
+	/* CPUID value */
+	u32 cpu;

/* DDR base_freq = 100 Mhz / 133 Mhz */
    u8 base_freq;