Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34662 )
Change subject: Documentation/binaries: Add AMD FSP documentation ......................................................................
Patch Set 12:
(6 comments)
Patch Set 12:
(6 comments)
Please make sure you're marking comments as resolved when you address them. Patches can no longer be merged until all comments are resolved, and while I don't mind marking one as resolved before merging, there are way too many comments in this patch set for anyone to deal with.
I'm doing it so. Currently only PS 11 has 2 comments unresolved... because I asked back clarification and have not yet resolved it. All else is resolved.
https://review.coreboot.org/c/coreboot/+/34662/12/Documentation/binaries/amd... File Documentation/binaries/amd/AMD_FSP_family_17h.md:
https://review.coreboot.org/c/coreboot/+/34662/12/Documentation/binaries/amd... PS12, Line 13: have
has
Done
https://review.coreboot.org/c/coreboot/+/34662/12/Documentation/binaries/amd... PS12, Line 14: v8
I'm not sure what AGESA v8 was. […]
AKA AGESA v8 as I understand it. I could also say "previous AGESA" if you prefer.
https://review.coreboot.org/c/coreboot/+/34662/12/Documentation/binaries/amd... PS12, Line 20: tell
tells the
Done
https://review.coreboot.org/c/coreboot/+/34662/12/Documentation/binaries/amd... PS12, Line 35: GESA has some DXE code, FSP does not \ : So required code was moved within AGESA from DXE phase to PEI phase.
So this is no longer an FSP difference, right?
When you put it this way, I guess you are right... will remove.
https://review.coreboot.org/c/coreboot/+/34662/12/Documentation/binaries/amd... PS12, Line 37: urrently all code is being landed in FSP-M due to AGESA dependencies. : However it's intended that some code will land in FSP-S in the future.
If we're initializing PCIe in FSP-S, this is no longer true, correct?
Currently we are initializing (not enumeration) PCIe in FSP-M, and that is a major dependency that Alex is having problems to break. He wants it in FSP-S (to conform with Intel FSP), but currently it needs to be done before he can report memory available. I'll convert this in to new #2 item to make it clear that this IS the difference I was talking... not really the DXE/PEI issue.
https://review.coreboot.org/c/coreboot/+/34662/12/Documentation/binaries/amd... PS12, Line 45: does
remove 'does'
Done