Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74804 )
Change subject: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses ......................................................................
soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses
This ports commit 8c28e51a16e1 ("soc/amd/picasso: fix host bridge bus numbers") back to Stoneyridge so that the correct number of PCI buses gets reported from PCI0's _CRS method. The MCFG ACPI table already had the correct last bus number.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I40121ab0e0438281192b6a0bec8dbecdc1749379 --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 1 file changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/74804/1
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index 6a7ed2e..dad8aaa 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -111,6 +111,11 @@ Local0 -= TOM1 MM1L = Local0
+ CreateWordField(CRES, ^PSB0._MAX, BMAX) + CreateWordField(CRES, ^PSB0._LEN, BLEN) + BMAX = CONFIG_ECAM_MMCONF_BUS_NUMBER - 1 + BLEN = CONFIG_ECAM_MMCONF_BUS_NUMBER + Return (CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */