[coreboot-gerrit] [XS] Change in coreboot[main]: sb/intel/bd82x6x/lpc: Enable more clock gatings

[Patrick Rudolph (Code Review)]

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79146?usp=email )

Change subject: sb/intel/bd82x6x/lpc: Enable more clock gatings
......................................................................

sb/intel/bd82x6x/lpc: Enable more clock gatings

Follow BWG and enable dynamic clock gating for all devices.

- Enable SMBUS clock gating
- Enable SATA clock gating

TEST: Lenovo X220 still boots over SATA.

Change-Id: I50970117ddcf8d39796426a19c1a6b57e5b1e690
Signed-off-by: Patrick Rudolph 
---
M src/southbridge/intel/bd82x6x/lpc.c
1 file changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/79146/1

diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c
index 0cf7b9c..eb8d35d 100644
--- a/src/southbridge/intel/bd82x6x/lpc.c
+++ b/src/southbridge/intel/bd82x6x/lpc.c
@@ -361,8 +361,10 @@
    reg16 |= (1 << 11);
    pci_write_config16(dev, GEN_PMCON_1, reg16);

+	/* DMI clock gating */
    pch_iobp_update(0xEB007F07, ~0U, (1 << 31));
    pch_iobp_update(0xEB004000, ~0U, (1 << 7));
+	/* PCIe clock gating */
    pch_iobp_update(0xEC007F07, ~0U, (1 << 31));
    pch_iobp_update(0xEC004000, ~0U, (1 << 7));

@@ -378,12 +380,17 @@
    reg32 &= ~(1 << 20);
    reg32 |= (1 << 19);
    reg32 |= (1 << 0);
+	reg32 |= (1 << 5);
    reg32 |= (0xf << 1);
    RCBA32(CG) = reg32;

RCBA32_OR(0x38c0, 0x7);
    RCBA32_OR(0x36d4, 0x6680c004);
    RCBA32_OR(0x3564, 0x3);
+
+	/* SATA clock gating */
+	pch_iobp_update(0xEA007F07, ~0U, (1 << 31));
+	pch_iobp_update(0xEA004000, ~0U, (1 << 7));
 }

static void pch_set_acpi_mode(void)