[coreboot-gerrit] Change in coreboot[master]: soc/intel/cmn/lpc: Add APIs to enable/disable LPC write protect (WP)

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/63687 )

Change subject: soc/intel/cmn/lpc: Add APIs to enable/disable LPC write protect (WP)
......................................................................

soc/intel/cmn/lpc: Add APIs to enable/disable LPC write protect (WP)

This patch implements two APIs to perform LPC/eSPI write protect enable/
disable operation using PCI configuration space register 0xDC
(BIOS Controller).

BUG=b:211954778
TEST=Able to build and boot google/redrix to OS.

Signed-off-by: Subrata Banik 
Change-Id: I8ce831218025a1d682ea2ad6be76901b0345b362
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63687
Tested-by: build bot (Jenkins) 
Reviewed-by: Lean Sheng Tan 
---
M src/soc/intel/common/block/include/intelblocks/lpc_lib.h
M src/soc/intel/common/block/lpc/lpc_def.h
M src/soc/intel/common/block/lpc/lpc_lib.c
3 files changed, 30 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Lean Sheng Tan: Looks good to me, approved

diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
index 3590852..7d03367 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
@@ -99,4 +99,8 @@
    				    unsigned long current,
    				    struct acpi_rsdp *rsdp);
 const uint8_t *lpc_get_pic_pirq_routing(size_t *num);
+/* Enable LPC Write Protect. */
+void lpc_enable_wp(void);
+/* Disable LPC Write Protect. */
+void lpc_disable_wp(void);
 #endif /* _SOC_COMMON_BLOCK_LPC_LIB_H_ */
diff --git a/src/soc/intel/common/block/lpc/lpc_def.h b/src/soc/intel/common/block/lpc/lpc_def.h
index ab9f2018..47697ca 100644
--- a/src/soc/intel/common/block/lpc/lpc_def.h
+++ b/src/soc/intel/common/block/lpc/lpc_def.h
@@ -26,6 +26,7 @@
 #define LPC_BIOS_CNTL			0xdc
 #define  LPC_BC_BILD			(1 << 7) /* BILD */
 #define  LPC_BC_LE			(1 << 1) /* LE */
+#define  LPC_BC_WPD			(1 << 0) /* WPD */
 #define  LPC_BC_EISS			(1 << 5) /* EISS */
 #define LPC_PCCTL			0xE0 /* PCI Clock Control */
 #define  LPC_PCCTL_CLKRUN_EN		(1 << 0)
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index 654dcea..cdaeae1 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -195,6 +195,31 @@
    lpc_set_bios_control_reg(LPC_BC_EISS);
 }

+static void lpc_configure_write_protect(bool status)
+{
+	const pci_devfn_t dev = PCH_DEV_LPC;
+	uint8_t bios_cntl;
+
+	bios_cntl = pci_read_config8(dev, LPC_BIOS_CNTL);
+	if (status)
+		bios_cntl &= ~LPC_BC_WPD;
+	else
+		bios_cntl |= LPC_BC_WPD;
+	pci_write_config8(dev, LPC_BIOS_CNTL, bios_cntl);
+}
+
+/* Enable LPC Write Protect. */
+void lpc_enable_wp(void)
+{
+	lpc_configure_write_protect(true);
+}
+
+/* Disable LPC Write Protect. */
+void lpc_disable_wp(void)
+{
+	lpc_configure_write_protect(false);
+}
+
 /*
 * Set LPC Serial IRQ mode.
 */

2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.