Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57273 )
Change subject: mb/google/brya/variants/brask: Enable PCIE port 7 for Ethernet ......................................................................
mb/google/brya/variants/brask: Enable PCIE port 7 for Ethernet
Enable PCIE port 7 using clk 6 for RTL8125 Ethernet
BUG=b:193750191 BRANCH=None TEST=build pass
Signed-off-by: David Wu david_wu@quanta.corp-partner.google.com Change-Id: Ic60a66dbd6ad87cf9c0de85ca7df4d854c371bf5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57273 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Tim Wawrzynczak twawrzynczak@chromium.org --- M src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb 1 file changed, 8 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved
diff --git a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb index d19f627..cc6664c 100644 --- a/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/brask/devicetree.cb @@ -125,6 +125,14 @@ end device ref heci1 on end device ref sata on end + device ref pcie_rp7 on + # Enable PCIE 7 using clk 6 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #PCIE7 RTL8125 Ethernet NIC device ref pcie_rp8 on # Enable SD Card PCIE 8 using clk 3 register "pch_pcie_rp[PCH_RP(8)]" = "{