build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45759 )
Change subject: soc/intel/alderlake/ramstage: Do initial SoC commit till ramstage ......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45759/7/src/soc/intel/alderlake/fsp... File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/45759/7/src/soc/intel/alderlake/fsp... PS7, Line 216: if (config->SataPortsEnableDitoConfig[i]) { suspect code indent for conditional statements (16, 32)