[coreboot-gerrit] [S] Change in coreboot[master]: soc/nvidia/tegra210: Fix flushing SPI fifo

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/70137 )

Change subject: soc/nvidia/tegra210: Fix flushing SPI fifo
......................................................................

soc/nvidia/tegra210: Fix flushing SPI fifo

This will avoid clearing the other bits in fifo_status.

Change-Id: I7917b3f8d9af6056ed872b7e48cef9c3deba5119
Signed-off-by: Arthur Heymans 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70137
Tested-by: build bot (Jenkins) 
Reviewed-by: Julius Werner 
---
M src/soc/nvidia/tegra210/spi.c
1 file changed, 16 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Julius Werner: Looks good to me, approved

diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c
index 0f38df2..e6f667a 100644
--- a/src/soc/nvidia/tegra210/spi.c
+++ b/src/soc/nvidia/tegra210/spi.c
@@ -331,7 +331,7 @@

uint32_t fifo_status = read32(&spi->regs->fifo_status);
    fifo_status |= flush_mask;
-	write32(&spi->regs->fifo_status, flush_mask);
+	write32(&spi->regs->fifo_status, fifo_status);

while (read32(&spi->regs->fifo_status) & flush_mask)
    	;