Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 20:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48340/20/src/soc/intel/alderlake/ch... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/20/src/soc/intel/alderlake/ch... PS20, Line 361: inline static inline
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/17/src/soc/intel/alderlake/ro... PS17, Line 48: PCH_PCIE_RP
If CPU root ports never wanted CLKREQ, we don't have to add flags for ever CPU root port. […]
Why is that? CPU root ports should be very similar to PCH root ports. Use of CLKREQ depends upon the use case and the device being attached to it. I don't see anything that would prevent a CPU root port from using CLKREQ. Is there something in EDS/PDG that prohibits this?